45 ms·

All that stuff is emulated in microcode. And while counting architectural registers is something, in reality modern out-of-order processors do something called

by ppg677 6y ago

All that stuff is emulated in microcode. And while counting architectural registers is something, in reality modern out-of-order processors do something called "register renaming" so that more registers can be used on-the-fly as it dynamically creates a data flow dependency graph. Yes, inside each processor.

colejohnson66 6y ago
There have been attempts to move the register renaming out of the processor and into the program through VLIW architectures such as the Itanium, but it failed because (1) they require “sufficiently smart compilers” that weren’t available in the day, and (2) putting it in the silicon allows new architecture revisions to benefit older programs (putting it in code means it can’t benefit from newer register renaming algorithms without a recompile). Also, if it’s in the silicon and there’s a bug in the algorithm, a microcode update can fix it for everyone. If the bug was in the compiler, you’d need to recompile everything to fix it.
- imtringued 6y ago
  The only successful VLIW architectures run JIT compilers on an existing ISA. Transmeta did this for x86 but Intel brought them to court them which gave Intel time to release superior chips (through superior manufacturing). The other example is Nvidia's Project Denver.
  - kllrnohj 6y ago
    A very debatable level of "successful" on that. It shipped in a product, yes, but it wasn't very good either. It ran ARM code, but not very well, and was a horrible nightmare to work on. The JIT'd aspect completely breaks profilers. ie, what do you mean this simple field access took 20ms?? Oh, because the CPU wasn't running my code, it just silently went out to lunch to JIT some random shit, cool, thanks. There's then also the questionable security design of a globally read/write/executable chunk of memory where security is "enforced" by the JIT which is a complex bit of microcode, totally nothing can go wrong there... It's only noteworthy "feature" was that it was able to ship ARMv8 support before ARM had a proper ARMv8 CPU design. Time to market for a new ISA was fast, but that's about it.
    - tambre 6y ago
      Project Denver lives on in NVIDIA's Carmel cores shipping in Tegra 194 (Xavier) chips today. Though they seem to be giving up on it, as they'll be using Cortex "Hercules" A78 cores in the successor named Orin.
  - SomeoneFromCA 6y ago
    Russian Elbrus machines (VLIW afaik) run Linux natively.

by ppg677 6y ago

colejohnson66 6y ago

There have been attempts to move the register renaming out of the processor and into the program through VLIW architectures such as the Itanium, but it failed because (1) they require “sufficiently smart compilers” that weren’t available in the day, and (2) putting it in the silicon allows new architecture revisions to benefit older programs (putting it in code means it can’t benefit from newer register renaming algorithms without a recompile). Also, if it’s in the silicon and there’s a bug in the algorithm, a microcode update can fix it for everyone. If the bug was in the compiler, you’d need to recompile everything to fix it.

imtringued 6y ago
The only successful VLIW architectures run JIT compilers on an existing ISA. Transmeta did this for x86 but Intel brought them to court them which gave Intel time to release superior chips (through superior manufacturing). The other example is Nvidia's Project Denver.
- kllrnohj 6y ago
  A very debatable level of "successful" on that. It shipped in a product, yes, but it wasn't very good either. It ran ARM code, but not very well, and was a horrible nightmare to work on. The JIT'd aspect completely breaks profilers. ie, what do you mean this simple field access took 20ms?? Oh, because the CPU wasn't running my code, it just silently went out to lunch to JIT some random shit, cool, thanks. There's then also the questionable security design of a globally read/write/executable chunk of memory where security is "enforced" by the JIT which is a complex bit of microcode, totally nothing can go wrong there... It's only noteworthy "feature" was that it was able to ship ARMv8 support before ARM had a proper ARMv8 CPU design. Time to market for a new ISA was fast, but that's about it.
  - tambre 6y ago
    Project Denver lives on in NVIDIA's Carmel cores shipping in Tegra 194 (Xavier) chips today. Though they seem to be giving up on it, as they'll be using Cortex "Hercules" A78 cores in the successor named Orin.
- SomeoneFromCA 6y ago
  Russian Elbrus machines (VLIW afaik) run Linux natively.