4 ms·
This is undoubtedly why they launched the Mac Mini today. They can ramp up a lot more power in that machine without a battery and with a larger, active cooler.
by hajile 6y ago
This is undoubtedly why they launched the Mac Mini today. They can ramp up a lot more power in that machine without a battery and with a larger, active cooler.
I'm much more interested in actual benchmarks. AMD has mostly capped their APU performance because DDR4 just can't keep the GPU fed (why the last 2 generations of consoles went with very wide GDDR5/6). Their solution is obviously Infinity Cache where they add a bunch of cache on-die to reduce the need to go off-chip. At just 16B transistors, Apple obviously didn't do this (at 6 transistors per SRAM cell, there's around 3.2B transistors in just 64MB of cache).
- rbanffy 6y agoWith the DRAM this close, it can probably be very fast. Did they say anything about bus or bandwidth?
- saidajigumi 6y agoAnandTech speculates on a 128-bit DRAM bus[1], but AFAIK Apple hasn't revealed rich details about the memory architecture. It'll be interesting to see what the overall memory bandwidth story looks like as hardware trickles out. [1] https://www.anandtech.com/show/16226/apple-silicon-m1-a14-deep-dive https://www.anandtech.com/show/16226/apple-silicon-m1-a14-de...
- rbanffy 6y agoApple being Apple, we won't know much before someone grinds down a couple chips to reveal what the interconnections are, but if you are feeding GPUs along with CPUs, a wider memory bus between DRAM and the SoC cache makes a lot of sense.
- deleted 6y ago[deleted]
- ineedasername 6y agoOkay, probably a stupid question, but solid state memory can be pretty dense: why don't we have huge caches, like a 1GB cache? As I understand it, cache memory doesn't put off heat like the computational part of the chip does, so heat dissipation probably wouldn't increase much with a larger chip package.
- coryrc 6y agoCost. Area is what you pay for (at a given transistor size).
- semi-extrinsic 6y agoWell, the latest AMD Epyc has 256 MB L3 cache, so we're getting there.
- gameswithgo 6y agobut any given core only has access to 16 soon to be 32mb
- fulafel 6y agoin Zen 1 and Zen 2, cores have direct or indirect access to the shared L3 cache in the same CCX. In the cross-CCX case the neighboring CCX cache can be accessed over the in-package interconnect without going through system DRAM.
- samoa42 6y agothis! when i started with computers, they had a few KB of L2 cache, L3 did not exist. Main Memory was a few MB.
- atq2119 6y agoSRAM is 6 transistors per bit, so you're taking about 48 billion transistors there, and that's ignoring the overhead of all the circuits around the cells themselves. DRAM is denser, but difficult to build on the same process as logic. That said, with chiplets and package integration becoming more common, who knows... One die of DRAM as large cache combined with a logic die may start to make more sense. It's certainly something people have tried before, it just didn't really catch on.
- Pet_Ant 6y ago> DRAM is denser, but difficult to build on the same process as logic. What makes it so difficult to have on the same chip?
- xbar 6y agoI am looking forward to compile time benchmarks for Chromium. I think this chip and SoC architecture may make the Air a truly fantastic dev box for larger projects.