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ARM is smaller due to simpler instruction decoders mostly, which leaves more room for a huge cache in the transistor budget. I am hoping Apple does this with t

by api 6y ago

ARM is smaller due to simpler instruction decoders mostly, which leaves more room for a huge cache in the transistor budget. I am hoping Apple does this with their desktop chips: basically take the fastest phone/tablet processor, give it better thermals, and pump up the cache. That would be an easy path to beating Intel on a laptop.

nicoburns 6y ago
My understanding was that large cache was mostly a cost tradeoff, and that there's no technical reason why x86 processors couldn't do this too. I believe Apple's A-series chips already have a huge cache which is a big part of why they are so fast.
- opencl 6y ago
  Cost/die size is part of the consideration especially for L3 but with L1 and L2 it is much more about latency than cost: bigger caches will have higher latency than smaller ones. That's the entire reason for the multi-level cache hierarchy to exist in the first place. Graviton2 doesn't even have a particularly large total amount of cache, the only part of the cache system that's bigger than both AMD and Intel is the L1D. L1I is the same as AMD, L2 is same as Intel, L3 is smaller than both (talking about current-gen server chips). That L1D can indeed make a big difference in certain workloads though. The L3 is actually pretty small for how many cores there are, ARM recommends 1-2MB/core for the N1 cores in the Graviton2 and it has 512KB/core. AMD has 4MB per core in Zen2 albeit with a slightly weird setup where the L3 is localized to 4 core clusters.
  - savanx 6y ago
    Disclosure: I work at AWS. Graviton2 has 64KB L1 caches and 1MB L2 cache per vCPU, with a 32MB LLC. Source: https://youtu.be/4jImmuMqnwc?t=1111 https://youtu.be/4jImmuMqnwc?t=1111
- deleted 6y ago
  [deleted]
- vondur 6y ago
  Ryzen CPU's seem to have a decent amount of cache's built in: Level 1 cache size 12 x 32 KB 8-way set associative instruction caches 12 x 32 KB 8-way set associative data caches Level 2 cache size 12 x 512 KB 8-way set associative unified caches Level 3 cache size 4 x 16 MB 16-way set associative shared caches

by api 6y ago

nicoburns 6y ago

My understanding was that large cache was mostly a cost tradeoff, and that there's no technical reason why x86 processors couldn't do this too. I believe Apple's A-series chips already have a huge cache which is a big part of why they are so fast.

opencl 6y ago
Cost/die size is part of the consideration especially for L3 but with L1 and L2 it is much more about latency than cost: bigger caches will have higher latency than smaller ones. That's the entire reason for the multi-level cache hierarchy to exist in the first place. Graviton2 doesn't even have a particularly large total amount of cache, the only part of the cache system that's bigger than both AMD and Intel is the L1D. L1I is the same as AMD, L2 is same as Intel, L3 is smaller than both (talking about current-gen server chips). That L1D can indeed make a big difference in certain workloads though. The L3 is actually pretty small for how many cores there are, ARM recommends 1-2MB/core for the N1 cores in the Graviton2 and it has 512KB/core. AMD has 4MB per core in Zen2 albeit with a slightly weird setup where the L3 is localized to 4 core clusters.
- savanx 6y ago
  Disclosure: I work at AWS. Graviton2 has 64KB L1 caches and 1MB L2 cache per vCPU, with a 32MB LLC. Source: https://youtu.be/4jImmuMqnwc?t=1111 https://youtu.be/4jImmuMqnwc?t=1111
deleted 6y ago
[deleted]
vondur 6y ago
Ryzen CPU's seem to have a decent amount of cache's built in: Level 1 cache size 12 x 32 KB 8-way set associative instruction caches 12 x 32 KB 8-way set associative data caches Level 2 cache size 12 x 512 KB 8-way set associative unified caches Level 3 cache size 4 x 16 MB 16-way set associative shared caches