5 ms·

To understand RISC, ignore the acronym it stands for, instead just think fixed-instruction, load-store architecture. That's what RISC really means today. No va

To understand RISC, ignore the acronym it stands for, instead just think fixed-instruction, load-store architecture. That's what RISC really means today. No variable-length instructions. No arithmetic instructions that can take memory operands, shift them, and update their address at the same time.

userbinator 6y ago
...and even ARM breaks instructions into uops, just like x86.
- mhh__ 6y ago
  Of course it does. The level of abstraction required for modern pipelining and OOo scheduling is still beneath ARM. I'm not that familiar with the details of arm on paper but it's not that low level by research standards.
dragontamer 6y ago
> No variable-length instructions AESE / AESMC (AES Encode, AES Mix-columns) are an instruction pair in modern ARM chips in which the pair runs as a singular fused macro-op. That is to say, a modern ARM chip will see "AESE / AESMC", and then fuse the two instructions and execute them simultaneously for performance reasons. Almost every "AESE" encode instruction must be followed up with AESMC (mix columns), so this leads to a significant performance increase for ARM AES instructions.
elygre 6y ago
Someone once explained it like “not a reduced set, but a set of reduced instructions”. Not r(is)c, but (ri)sc. Pretty much what you say, I just liked the way of describing it.
- FullyFunctional 6y ago
  It seems to me people are ignoring that the C stands for Complexity. What's reduced is Complexity of the instruction set, not the size of it (or even the instructions themselves). In the context of the coinage of the term, they almost certainly could have called it "microcode-free ISA", but it wouldn't have sounded as cool.
  - mavhc 6y ago
    Doesn't the C stand for Computer?
    - FullyFunctional 6y ago
      Oops I'm wrong about the name but not about the spirit. This is the original paper: https://dl.acm.org/doi/pdf/10.1145/641914.641917 https://dl.acm.org/doi/pdf/10.1145/641914.641917
  - andromeduck 6y ago
    Is ARM even microcode free these days?
    - arthurcolle 6y ago
      I dont think so
Joker_vD 6y ago
What is with variable-length instruction aversion? Why is it better to load a 32-bit immediate with two 4-byte instructions (oh, and splitting it in 12/20 bit parts is non-intuitive because of sign extension, thanks RISC V authors) than with one 5-byte instuction?
- sharpneli 6y ago
  Fixed width instructions allow trivial parallel instruction decoding. With variable length instructions one must decode a previous one to figure out where the next one will start.
  - scottlamb 6y ago
    > With variable length instructions one must decode a previous one to figure out where the next one will start. People said the same thing about text encodings. Then UTF-8 came along. Has anyone applied the same idea to instruction encoding?
    - Someone 6y ago
      That would eat precious bits in each instruction (one in each byte, if one only indicates ‘first’ or ‘last’ bytes of each instruction). It probably is better to keep the “how long is this instruction” logic harder and ‘waste’ logic on the decoder.
      - scottlamb 6y ago
        That doesn't sound so bad to me, in comparison to fixed-size instructions. One bit in each byte gone to have the most common instructions take one byte instead of four. I can imagine that allowing much denser code overall. Or it could be one bit out of every pair of bytes, to support 2-, 4-, and 6-byte instructions. I don't know much about ARM Thumb-2, except that it does 2- or 4-byte instructions, so clearly someone thought this much was a good idea. Instruction encodings are below my usual abstraction layer; I'm just speculating...
wolfgke 6y ago
> think fixed-instruction, l[...]. That's what RISC really means today. > No variable-length instructions. So, ARM is not a RISC instruction set, because T32 (Thumb-2) instruction can be 2 or 4 bytes long. Similarly, RISC-V has variable-length instructions for extensibility. See p. 8ff of https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf https://github.com/riscv/riscv-isa-manual/releases/download/... (section "Expanded Instruction-Length Encoding").

userbinator 6y ago

...and even ARM breaks instructions into uops, just like x86.

mhh__ 6y ago
Of course it does. The level of abstraction required for modern pipelining and OOo scheduling is still beneath ARM. I'm not that familiar with the details of arm on paper but it's not that low level by research standards.

dragontamer 6y ago

> No variable-length instructions AESE / AESMC (AES Encode, AES Mix-columns) are an instruction pair in modern ARM chips in which the pair runs as a singular fused macro-op. That is to say, a modern ARM chip will see "AESE / AESMC", and then fuse the two instructions and execute them simultaneously for performance reasons. Almost every "AESE" encode instruction must be followed up with AESMC (mix columns), so this leads to a significant performance increase for ARM AES instructions.

elygre 6y ago

Someone once explained it like “not a reduced set, but a set of reduced instructions”. Not r(is)c, but (ri)sc. Pretty much what you say, I just liked the way of describing it.

FullyFunctional 6y ago
It seems to me people are ignoring that the C stands for Complexity. What's reduced is Complexity of the instruction set, not the size of it (or even the instructions themselves). In the context of the coinage of the term, they almost certainly could have called it "microcode-free ISA", but it wouldn't have sounded as cool.
- mavhc 6y ago
  Doesn't the C stand for Computer?
  - FullyFunctional 6y ago
    Oops I'm wrong about the name but not about the spirit. This is the original paper: https://dl.acm.org/doi/pdf/10.1145/641914.641917 https://dl.acm.org/doi/pdf/10.1145/641914.641917
- andromeduck 6y ago
  Is ARM even microcode free these days?
  - arthurcolle 6y ago
    I dont think so

Joker_vD 6y ago

What is with variable-length instruction aversion? Why is it better to load a 32-bit immediate with two 4-byte instructions (oh, and splitting it in 12/20 bit parts is non-intuitive because of sign extension, thanks RISC V authors) than with one 5-byte instuction?

sharpneli 6y ago
Fixed width instructions allow trivial parallel instruction decoding. With variable length instructions one must decode a previous one to figure out where the next one will start.
- scottlamb 6y ago
  > With variable length instructions one must decode a previous one to figure out where the next one will start. People said the same thing about text encodings. Then UTF-8 came along. Has anyone applied the same idea to instruction encoding?
  - Someone 6y ago
    That would eat precious bits in each instruction (one in each byte, if one only indicates ‘first’ or ‘last’ bytes of each instruction). It probably is better to keep the “how long is this instruction” logic harder and ‘waste’ logic on the decoder.
    - scottlamb 6y ago
      That doesn't sound so bad to me, in comparison to fixed-size instructions. One bit in each byte gone to have the most common instructions take one byte instead of four. I can imagine that allowing much denser code overall. Or it could be one bit out of every pair of bytes, to support 2-, 4-, and 6-byte instructions. I don't know much about ARM Thumb-2, except that it does 2- or 4-byte instructions, so clearly someone thought this much was a good idea. Instruction encodings are below my usual abstraction layer; I'm just speculating...

wolfgke 6y ago

> think fixed-instruction, l[...]. That's what RISC really means today. > No variable-length instructions. So, ARM is not a RISC instruction set, because T32 (Thumb-2) instruction can be 2 or 4 bytes long. Similarly, RISC-V has variable-length instructions for extensibility. See p. 8ff of https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf https://github.com/riscv/riscv-isa-manual/releases/download/... (section "Expanded Instruction-Length Encoding").