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I especially liked the section on DDR memory PCB routing and how it is less complicated than people make it out to be. At least for this application. Makes one

by corty 6y ago

I especially liked the section on DDR memory PCB routing and how it is less complicated than people make it out to be. At least for this application. Makes one want to try something like this

ianhowson 6y ago
Huh. I almost missed that, but can confirm. On a past project we had two DDR RAMs and a NOR Flash on the same bus. There was one hardware engineer, and he laid out the memory subsystem in about a day. (The power supplies were dramatically more complicated.) It almost worked first time. I noticed about one memory error per day per device, which I repro'd with repeated `md5sum /tmp/largefile`. We just dropped the clock rate in U-Boot. Failed devices? Heat it up with a hot air gun for a while. Fixed 90% of them. Still doesn't work? Throw it away. There are no mysteries, just stuff you don't know yet.
joezydeco 6y ago
The part not discussed is how many PCB layers (signal, ground, more signal, more ground, etc) you need when laying down DDR. If you are playing with a 2x2" EVK then 8 or 10 layers isn't a budgetary problem. When the board starts getting larger it's now it's a huge cost adder as opposed to low speed 2-layer PCB. This is why designers switch to doing it with SOMs. The SOM can be a high-speed part and the carrier PCB is cheap and slow.
- rcxdude 6y ago
  He mentioned all the PCB designs were using 4 layer, which is pretty cheap even in prototype quantities.
  - cushychicken 6y ago
    Choosing a four layer stackup was a really instructive point for the purposes of his blog post, but kind of a bad rule of thumb to carry forward on a professional level. PCBs are built in a sandwich stack. The middle dielectric layer, or "prepreg", is way thicker than the dielectric layers in the outer layers. This doesn't seem like a big deal, but for the speeds that a DDR interface runs at, it creates a higher impedance return loop for whatever you end up routing on layer 3. (Typically DQs, in my experience.) You can avoid this entirely by building with a six layer stackup, and routing your DRAM signals on layers 1/2/3, keeping layer 2 as an unbroken ground plane. The result: nice, low impedance return tracks. Yes, Jay is right - most of the time, this doesn't create problems. But when it does, it's pretty challenging to fix without a board spin, and when you're doing this professionally, that loses you time, creates risk, and is generally hella stressful.
    - joezydeco 6y ago
      Well said. And we're not even mentioning what happens when you start adding other criss-crossing traces for parallel LCDs and cameras into the mix. Those usually creep into the 30-40 MHz range, 18-24 lines per device with no differential lines. And I haven't even thought about USB-C yet. And you still need to pass radiated emissions testing. Even those right-angle DIMM connectors for the SOMs spray RF noise everywhere when you put video on them.
      - cushychicken 6y ago
        cough cough METAL ENCLOSURE cough cough :)
        joezydeco 6y ago
        (injection molded ABS with thin-film deposition aluminum)
        cushychicken 6y ago
        :o
cushychicken 6y ago
The important caveat of that claim: it's less complicated than you think, for point to point topologies. I strongly prefer point to point designs just for their simplicity. It makes it way easier to fix any SI or timing issues through write leveling/launch calibration adjustments. Once you get into flyby or T-routing topologies - good luck!

by corty 6y ago

I especially liked the section on DDR memory PCB routing and how it is less complicated than people make it out to be. At least for this application. Makes one want to try something like this

ianhowson 6y ago

Huh. I almost missed that, but can confirm. On a past project we had two DDR RAMs and a NOR Flash on the same bus. There was one hardware engineer, and he laid out the memory subsystem in about a day. (The power supplies were dramatically more complicated.) It almost worked first time. I noticed about one memory error per day per device, which I repro'd with repeated `md5sum /tmp/largefile`. We just dropped the clock rate in U-Boot. Failed devices? Heat it up with a hot air gun for a while. Fixed 90% of them. Still doesn't work? Throw it away. There are no mysteries, just stuff you don't know yet.

joezydeco 6y ago

The part not discussed is how many PCB layers (signal, ground, more signal, more ground, etc) you need when laying down DDR. If you are playing with a 2x2" EVK then 8 or 10 layers isn't a budgetary problem. When the board starts getting larger it's now it's a huge cost adder as opposed to low speed 2-layer PCB. This is why designers switch to doing it with SOMs. The SOM can be a high-speed part and the carrier PCB is cheap and slow.

rcxdude 6y ago
He mentioned all the PCB designs were using 4 layer, which is pretty cheap even in prototype quantities.
- cushychicken 6y ago
  Choosing a four layer stackup was a really instructive point for the purposes of his blog post, but kind of a bad rule of thumb to carry forward on a professional level. PCBs are built in a sandwich stack. The middle dielectric layer, or "prepreg", is way thicker than the dielectric layers in the outer layers. This doesn't seem like a big deal, but for the speeds that a DDR interface runs at, it creates a higher impedance return loop for whatever you end up routing on layer 3. (Typically DQs, in my experience.) You can avoid this entirely by building with a six layer stackup, and routing your DRAM signals on layers 1/2/3, keeping layer 2 as an unbroken ground plane. The result: nice, low impedance return tracks. Yes, Jay is right - most of the time, this doesn't create problems. But when it does, it's pretty challenging to fix without a board spin, and when you're doing this professionally, that loses you time, creates risk, and is generally hella stressful.
  - joezydeco 6y ago
    Well said. And we're not even mentioning what happens when you start adding other criss-crossing traces for parallel LCDs and cameras into the mix. Those usually creep into the 30-40 MHz range, 18-24 lines per device with no differential lines. And I haven't even thought about USB-C yet. And you still need to pass radiated emissions testing. Even those right-angle DIMM connectors for the SOMs spray RF noise everywhere when you put video on them.
    - cushychicken 6y ago
      cough cough METAL ENCLOSURE cough cough :)
      - joezydeco 6y ago
        (injection molded ABS with thin-film deposition aluminum)
        cushychicken 6y ago
        :o

cushychicken 6y ago

The important caveat of that claim: it's less complicated than you think, for point to point topologies. I strongly prefer point to point designs just for their simplicity. It makes it way easier to fix any SI or timing issues through write leveling/launch calibration adjustments. Once you get into flyby or T-routing topologies - good luck!