5 ms·
> 20 % IPC increase, 20 % higher perf/W on the same process, effectively double the cache size, and reduced memory latency. Absolute insanity from AMD. An incr
by baybal2 6y ago
> 20 % IPC increase, 20 % higher perf/W on the same process, effectively double the cache size, and reduced memory latency. Absolute insanity from AMD.
An increase like this wasn't something unexpected from a generational update back in nineties.
- dragontamer 6y agoBut this is an architectural tweak on the same node. Zen2 was 7nm TSMC, while Zen3 is 7+nm TSMC. TSMC must have optimized the heck out of their transistors to deliver such a large benefit. Or the AMD Zen 3 architecture really found some low-hanging fruit or something to grossly improve performance.
- bch 6y ago> low-hanging fruit or something to grossly improve performance. If there’s such a thing anymore I’d be fascinated to hear about it.
- pedrocr 6y agoAnandtech will have one of their detailed microarchitecture breakdowns at product availability day (November 5th).
- pedrocr 6y agoThe IPC increase seems to be coming from the microarchitecture, not the process. The Anandtech article includes a breakdown: https://images.anandtech.com/doci/16148/1%20Slide%206_575px.jpg https://images.anandtech.com/doci/16148/1%20Slide%206_575px.... +2.7% Cache Prefetching +3.3% Execution Engine +1.3% Branch Predictor +2.7% Micro-op Cache +4.6% Front End +4.6% Load/Store
- phkahler 6y agoNo silver bullet there, just small gains in a bunch of areas. Some of those may have been hard wins too.
- moonbas3 6y agoIn the slides it was still marked as 7nm without the +.
- brundolf 6y agoIt's much harder to do now