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That spec is just a draft, and still undergoing revision. Its close in spirit to a Scheme RFI (request for implementation). Until the consortium ratifies it (
by brandmeyer 6y ago
That spec is just a draft, and still undergoing revision. Its close in spirit to a Scheme RFI (request for implementation). Until the consortium ratifies it (ie, members state their intention to implement it), its just a wishlist. A well-reasoned wishlist, but a wishlist just the same.
- ncmncm 6y agoExactly the point: no popcount. It is just hard to imagine the thought process that would leave something as important as popcount to such a dodgy and long-delayed prospect; hard to imagine omitting it from the core instruction set, so that it is only ever implemented, if ever, in the most distended and expensive chips.
- brandmeyer 6y agoI think RISC-V isn't really targeting general-purpose machines. They are targeting special-purpose machines. Think Google TPU built from a RISC-V scalar unit + custom tensor unit. 64-bit flash controller without a multiplier or MMU, but with specialized instructions to accelerate error correction. Something to manage the DDR training at startup. Embedded security widgets. Things like that. This is a development machine announcement for the companies who are building such custom hardware.
- gnufx 6y agoThe sort of things being targetted by one effort are listed at https://shakti.org.in/processors.html https://shakti.org.in/processors.html whether or not that has anything to do with popcount. This SiFive one seems interesting for having the vector extension, though that hadn't been finalized the last I knew.
- msla 6y agoThe Pentium didn't include a popcount opcode. One wonders how such a crippled chip ever made it in the world.
- ncmncm 6y agoEverything has it now. The NSA demanded that any machine they use have it, going back to the '60s. For reasons.
- sitkack 6y agoIt isn't as if RISC-V implementors are precluded from extending or implementing the bitmanip spec.