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SiFive to Debut RISC-V PC for Developers Based on Freedom U740 Next-Gen SoC
- guerby 6y agoPress release: https://www.businesswire.com/news/home/20200914005108/en/SiFive-To-Introduce-New-RISC-V-Processor-Architecture-and-RISC-V-PC-at-Linley-Fall-Virtual-Processor-Conference https://www.businesswire.com/news/home/20200914005108/en/SiF...
- jagger27 6y agoBring it on. If Arm is the future of desktop computing, it'll need a competitor.
- klelatti 6y agoIndeed, plus a viable competitor is the best way to ensure Nvidia is a reasonable steward of the Arm ecosystem.
- mhh__ 6y agoThe likelihood of ARM sailing off into the distance and x86 disappearing is very slim. It's worth keeping in mind that they have more in common than you might think (i.e. RISC and CISC don't mean a huge amount any more when the old x86 instructions aren't used any more and ARM had/has a JavaScript instruction)
- giancarlostoro 6y agoSo if RISC-V adopts WASM would that give it an interesting edge? I'm not a hardware guy, all software, but definitely would love to see a little more diversity in consumer grade hardware.
- mhh__ 6y agoYou could standardize a WASM translator into any ISA (or a direct implementation hypothetically), but it wouldn't be particularly useful because WASM is designed to be nice (safe) to be run in the browser in a JIT environment. If you want diversity, and an introduction to truly Alien CPU designs I recommend taking a look at the Mill.
- deleted 6y ago[deleted]
- nsajko 6y agox86 has a quite variable instruction size, up to 15 bytes. So an x86 decoder will be more complicated than an ARM or RISC-V decoder. I'm pretty sure that means that designing performant IP is more difficult engineering-wise for x86.
- ncmncm 6y agoNo doubt, but it is already worked out. And it turns out to take up a remarkably small area of the die. So, unless it actually slows down execution, it is a small tax that is overwhelmed by benefits of volume production.
- aiilns 6y agoSorry for going off topic, but your comment confuses me. Doesn't "sail off into the distance" mean to disappear? But you're saying the opposite in your comment? My reasonibg being that when a ship sails off into the distance it disappears from view.
- athriren 6y agoYou read it right. I think they are saying it is unlikely ARM or x86 disappear, and that these instruction sets share some unexpected commonalities. They are not otherwise comparing/contrasting x86 and ARM, they are basically evaluating if either one seems likely to disappear and answering in their opinion: “no”.
- mhh__ 6y agoAs in sailing off leaving x86 behind
- brucehoult 6y ago"ARM has a Javascript instruction" is just misinformed. They have always had the FCVTZS instruction which converts a floating point number to an integer (just as every instruction set has). If the floating point number is too large to fit in an integer then the bottom 32 bits are returned. The new(ish) FJCVTZS does exactly the same operation except that if the floating point number it too large then the largest integer is always returned. The implementation complexity difference is just about zero. It just so happens that the new instruction fits what JavaScript wants while the old one fits what C wants. There is certainly nothing non-RISC about FJCVTZS. It's a perfectly simple instruction.
- mhh__ 6y agoSpeaking of competition, I was reading the Mill news board and apparently they were planning on taking a step up this summer but COVID meant they couldn't do it. (But they are still ticking along)
- pabs3 6y agoSadly the Mill is by no means an open ISA, mostly because of all the patents they are filing.
- mtsr 6y agoIn the current legal environment exported by the US, it might be better to have licensed patented technology. Otherwise one leaves opportunity for trolls to patent and sue companies in that space.
- happymellon 6y agoIsn't this the point of the Open Innovation Network?
- farseer 6y agoHave not seen any RISC-V offering from the Chinese yet. I wonder if SiFive will have any competition.
- krasin 6y agoHere you go: M5Stack tiny computer with a camera, LCD and RISC-V AI-capable Chinese chip (Kendryte K210). Available on Digikey for $26.50: https://www.digikey.com/products/en?keywords=K027&v=2221 https://www.digikey.com/products/en?keywords=K027&v=2221
- mhh__ 6y agoLast time I looked at it (few months ago) the K210 had absolutely awful documentation (datasheet was basically just a pinout) in English and Chinese. Not awful but for a high margin product I'd just use a US arm chip (e.g. LPCxx).
- deleted 6y ago[deleted]
- FullyFunctional 6y agoPlease note that it has a non-working MMU and is limited to 8 MB of DRAM. This is not the SBC you were looking for.
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- etaioinshrdlu 6y agoI wonder to what extent the digital logic design is open source. The RISC-V core ought to be, but what about the memory controller or PCIE root complex, (or USB3)? Those parts are also very important.
- gchadwick 6y agoJust because it's RISC-V doesn't mean it's open source. RISC-V is an open architecture so anyone can make an implementation but those implementations can be closed source. SiFive have released some open source stuff (https://github.com/sifive/freedom https://github.com/sifive/freedom) but the majority of their work is closed source IP. In a way they're quite similar to arm.
- userbinator 6y agoJust like ARM, the only thing standard is the core and there is massive (and almost always publicly undocumented) diversity of everything else.
- brandmeyer 6y agoNot just like ARM. You don't need a license to implement a RISC-V compatible machine. IIUC, you only need to pass a compliance test to brand your machine RISC-V and use the trademark.
- Taniwha 6y agoThere's not just one RISC-V core, one of the great things is that there are many, of varying complexity and performance. Some are very open source some are not. There's already GCC and clang support, linux is here too.
- gnufx 6y agoGCC doesn't have support for this system's vector unit in the development source as far as I can see. Does LLVM?
- nickik 6y agoIf this is anywhere reasonably price and has open firmware, I'm in.
- ncmncm 6y agoSigh. Still without the Bitmanip instructions. Meaning, no popcount :-P
- brandmeyer 6y agoThat spec is just a draft, and still undergoing revision. Its close in spirit to a Scheme RFI (request for implementation). Until the consortium ratifies it (ie, members state their intention to implement it), its just a wishlist. A well-reasoned wishlist, but a wishlist just the same.
- ncmncm 6y agoExactly the point: no popcount. It is just hard to imagine the thought process that would leave something as important as popcount to such a dodgy and long-delayed prospect; hard to imagine omitting it from the core instruction set, so that it is only ever implemented, if ever, in the most distended and expensive chips.
- brandmeyer 6y agoI think RISC-V isn't really targeting general-purpose machines. They are targeting special-purpose machines. Think Google TPU built from a RISC-V scalar unit + custom tensor unit. 64-bit flash controller without a multiplier or MMU, but with specialized instructions to accelerate error correction. Something to manage the DDR training at startup. Embedded security widgets. Things like that. This is a development machine announcement for the companies who are building such custom hardware.
- gnufx 6y agoThe sort of things being targetted by one effort are listed at https://shakti.org.in/processors.html https://shakti.org.in/processors.html whether or not that has anything to do with popcount. This SiFive one seems interesting for having the vector extension, though that hadn't been finalized the last I knew.
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