6 ms·

Why is RISC-V even so hyped up/successful? Other open ISAs precede it, and AFAIK the code density that RISC-V allows is disappointing considering the designers

• jdc 6y ago
  https://riscv.org/risc-v-genealogy/ https://riscv.org/risc-v-genealogy/ https://en.wikipedia.org/wiki/RISC-V#History https://en.wikipedia.org/wiki/RISC-V#History
• hajile 6y ago
  The code density beats ARMv8 (the best they could do with a fresh start do-over) and beats x86 too. They gave serious consideration to creating a compact instruction set that also doesn't cause the performance impacts seen in Thumb. There's various reasons for a new ISA. The most appealing right now is the patent pool. Most other open ISAs are explicitly patent encumbered (recent MIPS versions) or provide zero protection (openrisc). The chances of getting sued over RISCV seem very small until you start moving to non-ISA parts of the chip. For an ISA to succeed, the ISA itself is a distant second to the ecosystem as x86 shows so well. The amount of money an R&D being poured into RISCV would single-handedly be enough reason to adopt.
• messe 6y ago
  > the code density that RISC-V allows is disappointing considering the designers had an opportunity to start from scratch. IIRC the code density beats ARMv8 and x86_64 in most situations.
  • userbinator 6y ago
    They may have beaten the average compiler in x86 code density, but compilers aren't normally optimising for size and, as someone who has been writing x86 Asm for a long time, I can safely say that compiler output in general, even at max size opts, is far from the theoretical limit for x86 --- there is plenty of room for improvement there. On the other hand, RISCs are far more constrained in size optimisation. For an example of what I mean by x86 having a very high limit on code density, see https://news.ycombinator.com/item?id=15720923 https://news.ycombinator.com/item?id=15720923
    • messe 6y ago
      But that is part of the issue with x86. Steadily, the dense instructions of x86 have been neglected and become less performant. A perfect example of this is "rep movsb": up until I think a decade ago, Intel actually recommended against its use in their optimization manuals.
• vlmutolo 6y ago
  One concrete advantage RISCV has is its variable-length SIMD instruction set. The assembly instructions used for SIMD in RISCV can all operate on data sizes that are various powers of 2. All using the same instructions. You could even call it “SIMD with dynamically-sized data”. Right now, x86 needs one set of instructions for each SIMD data size. That’s why we have SSE, AVX, AVX512, etc. This introduces complexity for both hardware designers and software designers. You have to actively update software to work with newer chips with larger SIMD registers. In the proposed RISCV design, you wouldn’t have to. It would just work on all sizes.
  • lopmotr 6y ago
    Wow, I didn't realize how many of these x86 extensions are basically just SIMD with more and more registers, even going back to MMX in the 1990's. It somehow looks like they never planned ahead and just kept re-inventing a slightly bigger wheel. Great to see RISC-V does it in a unified way.
    • jlokier 6y ago
      To be fair to x86, each new generation of SIMD added new kinds of arithmetic & logic operations too, not just wider registers. RISC-V will need to do the same, so expect to see multiple versions of the "V" extension over time.
  • userbinator 6y ago
    Right now, x86 needs one set of instructions for each SIMD data size. If you look at the encodings, many of them are actually the same opcodes as the original MMX, but with prefixes. In the proposed RISCV design, you wouldn’t have to. It would just work on all sizes. That doesn't make sense --- how would the code know how much to increment pointers by, how many times to loop, alignment, etc. ? Unless they added some really un-RISC instructions to do automatic vectored operations (like if x86 had a REP ADDSB), I don't see how you wouldn't need to change software for changing SIMD widths.
    • monocasa 6y ago
• nickik 6y ago
  Because if you don't have an Open ISA you can't have an Open chip. That it, if you ever want to use open source hardware, you need an open source ISA. The RISC-V ISA with the Compressed extension is very competitive and often better pretty much anything else. RISC-V also has an innovative modular structure that allows it to be optimally used in many different industries while sharing a lot of code. The RISC-V Vector extension is really good and innovative. And so are some of the other extension.
• CameronNemo 6y ago
  >Other open ISAs precede it Do you have any in mind? From what I can tell even POWER is not as open as RISC-V. They only show schematics to their partners, not the public at large. https://en.wikipedia.org/wiki/OpenPOWER_Foundation#Openness https://en.wikipedia.org/wiki/OpenPOWER_Foundation#Openness
  • floatboth 6y ago
    This is about the ISA, and POWER ISA has indeed been made royalty-free recently. Schematics are about a particular microarchitecture, particular hardware implementation.
  • nsajko 6y ago
    OpenRISC, SPARC. POWER opened up only after RISC-V. Relevant Wikipedia page: https://en.wikipedia.org/wiki/Comparison_of_instruction_set_architectures https://en.wikipedia.org/wiki/Comparison_of_instruction_set_...
• cellularmitosis 6y ago
  are there any cheap risc-v sbc's yet? (or would this be the first?)