5 ms·

>so a feature with 3nm width Sigh, another post... another top comment not understanding that marketing name =/= any actual feature size anywhere on the chip.

• deleted 6y ago
  [deleted]
• jonplackett 6y ago
  and you're even getting downvoted for pointing it out...
  • nitrogen 6y ago
    The comment is not in the gray as I write this, but one tends to get better results generally by providing more information in a positive light, rather than simply saying that something is wrong without providing anything better. For example, if the parent comment had said, "Yes, the control over small numbers of atoms is interesting. Although transistors are going to be much larger than that, it is cool that the shrinking feature size allows [making up a "fact" here for demonstration purposes] edges of transistors to be sharper and a little closer together, so yields are higher for a given transistor density," then it would be more useful and better received. Also, remember "today's 10000": https://xkcd.com/1053/ https://xkcd.com/1053/
    • craftinator 6y ago
      But keep in mind, the parent poster likely didn't mean his words in a positive light. To portray them as such would be dishonest, which is unethical, confusing to all involved, and would lead to further confusion and incoherence as the conversation progressed.
  • jonplackett 6y ago
    and now I'm downvoted for pointing out that it's being pointed out... will it ever end? (it was in the grey when I commented, but i upvoted it so I think that brought it back into the black)
• Zenst 6y ago
  Exactly as one vendors 7nm may well contain more atoms than another vendors 10nm node. Node numbers mean nothing beyond comparing against comparable node's. Yes it's sad that node sizes are marketed in the same way the GHz race was at one stage and equally the disparity is greater when comparing nodes like for like.
• i-am-curious 6y ago
  This is unfortunately prevelant on most discussion forums. In many cases this correction is downvoted and buried deep.
• variaga 6y ago
  Once upon a time (the "Dennard Scaling Era") VLSI circuit design used the same relative geometry at different "feature sizes" - all dimensions of the design(wire width, wire spacing, gate length, gate pitch, ..., etc.) scaled by the same amount from generation to generation, so it was possible to completely specify the transistor layout with a single dimension (generally called 'L'), and derive all other measurements from that as a multiple of 'L'. Transistor density was proportional to 1/L^2. The measurement that was used originally for 'L' was the gate length. As designs shrunk below 40nm, it became impossible to shrink _every_ dimension proportionally. In particular, for planar silicon, gate length stops shrinking around ~30nm, but other things could still shrink. This meant that transistor density could still increase, but the relative geometry of wires/gates/spacing/etc. had to change, so it was no longer possible to specify the full geometry with a single number. But people liked the single number as a handy way of comparing processes, so marketing kept using it as a way to compare processes. The way they decided to do that was mostly to try and keep the proportionality between the transistor density of a process and 1/L^2. To the extent a "feature size" number of a process means anything, it means "the relative transistor density of this process is equivalent to what you would get if you had used the old (>40nm) geometry, and shrunk 'L' to the specified feature size". Even that relationship has degraded in recent years - now it's more like "we calculate the new feature size as the size of the previous process divided by sqrt(2)". Regardless, as stated in the parent, there is no single dimension of any recent process that corresponds to the '3nm' number. There's lots of resources online that describe this, but for an overview, you could start here (describes pre- and post-Dennard scaling): http://www.eng.biu.ac.il/temanad/files/2017/02/Lecture-4-Scaling.pdf http://www.eng.biu.ac.il/temanad/files/2017/02/Lecture-4-Sca...
  • ur-whale 6y ago
    Thanks for that explanation. What would be even more useful is an actual answer to the underlying question the OP seems to be making: how much further until one of the many dimensions you are talking about simply runs out of Si atoms? In other words, however "made-up" the 3nm marketing number may be, physics limits should still dictate a lower bound for it, and the OP seems to be wondering what that is.
• pottertheotter 6y ago
  Is there a dimension that can be used to compare across process tech since process node is now marketing and not gate length?
• XnoiVeX 6y ago
  It may not be generally true but _it is_ true for the smallest possible feature so it's not entirely incorrect either.
• solidasparagus 6y ago
  I hate when people complain about how uninformed everyone is, but don't put in even the tiniest amount of effort to help people become more informed. At the very least, include a link.
• googlryas 6y ago
  It would be nice if we could standardize on some physical feature size that we would then call everything equally. It's silly to have a measurement system which is calibrated differently for what should be apples-to-apples comparisons. Imagine if some car manufacturers listed the length of their car from the rear bumper to the steering wheel and other measured their lengths from the rear bumper to the front bumper.
• deleted 6y ago
  [deleted]
• ajnin 6y ago
  It's not fair to blame people for not knowing that "3nm" does not mean "3nm". Knowledge about measurement units is more prevalent than knowledge about marketing practices of semiconductor companies. Blame those misleading practices instead.
• not2b 6y ago
  The narrowest dimension of a FinFET is roughly the process node size, within a small factor, so my comment applies. In fact, the first FinFETs were actually narrower than the node size when they were introduced.