3 ms·
I'm sympathetic to this view and it was probably true in older generations of chips, but it turns out that instruction decode is a very small portion of die siz
by classichasclass 6y ago
I'm sympathetic to this view and it was probably true in older generations of chips, but it turns out that instruction decode is a very small portion of die size and power usage these days. The L2 probably uses more juice, for example. See Hirki et al.: https://www.usenix.org/system/files/conference/cooldc16/cooldc16-paper-hirki.pdf https://www.usenix.org/system/files/conference/cooldc16/cool...
- api 6y agoI think most of the power envelope difference these days is process node, with Intel chips usually lagging behind. That being said, I do think that if the same amount of performance engineering were dumped into ARM as has been put into X64 ARM would win. The simpler instruction encoding, less cruft (but not none!), and other modern characteristics would make that optimization go further. My concern as others have mentioned is lack of standardized interfaces and peripheral enumeration, leading to a lack of flexibility and the loss of ability to run alternative OSes and drivers. That can be fixed, but does anyone care enough to fix it?
- ben-schaaf 6y ago> I think most of the power envelope difference these days is process node, with Intel chips usually lagging behind. That hasn't been the case until quite recently. Before TSMC 7nm Intel was still at least on-par with everyone else. I think it boils down to arm chips being designed from the ground up with power usage in mind (with a fair number having slower low-power secondary cores and such), whereas Intel mostly expects your CPU to always be doing something even at idle.