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Again, the number filter mangled the title. The full title from the article is "Inside the 8086 processor, tiny charge pumps create a negative voltage". In the

Again, the number filter mangled the title. The full title from the article is "Inside the 8086 processor, tiny charge pumps create a negative voltage". In the interest of brevity, "processor" could be omitted or replaced with "chip."

kens 6y ago
I was wondering why the title ended up so bizarre. In any case, I'm the author if anyone has questions on the 8086 internals.
- allenrb 6y ago
  Hi Ken, love pretty much everything you write. Was wondering, is it correct to assume that all of the 8086 would have been laid out entirely by hand? Certainly special blocks like these charge pumps must have been, but was there any sort of design automation for things like the recently discussed register file?
  - pjc50 6y ago
    Followup question: when did we start describing these things with GDSII files (was there a GDSI?) rather than giant sheets of acetate?
  - kens 6y ago
    I think it was a mixture of hand layout and automated layout. There are a lot of places that do strange things to squeeze out every last bit of space, and I think this optimization was done by machine. For instance, long signal traces have a lot of twists and turns to be as close together as possible while avoiding obstacles and satisfying the design rules. Sometimes these signals do strange things like switching from poly wires to metal wires and back just so they can be a bit closer. These micro-optimizations don't seem like ones a human would make. Another thing I've noticed is between two revisions of the chip that have identical layout except for a few traces. On one chip a trace will have a jog that's two 90-degree turns. On the other chip, the same trace will have 45 degree bends. So the two traces are identical except for this short segment. I assume that the automated layout algorithm changed slightly, resulting in this change.
    - userbinator 6y ago
      On one chip a trace will have a jog that's two 90-degree turns. On the other chip, the same trace will have 45 degree bends. If the 45 degree one is the newer version, that might be a DFM optimisation - there is common folklore around PCB design that 90 or acute angles can cause various problems, with some hint of truth to it, but I suspect there are similar constraints in photolithography. If the sharp corner was causing yield losses, a newer revision would definitely address that.
      - dboreham 6y ago
        Electrons fly off as they try to take the 90 bend.
        amelius 6y ago
        Electrons in a typical circuit have a drift velocity that is very low (order of millimeters per hour). Of course, the electrons individually are very fast, but they are also almost as fast when there is no voltage applied.
        userbinator 6y ago
        There is a bit of truth to that --- sharp corners are more prone to electromigration: https://en.wikipedia.org/wiki/Electromigration#Via_arrangements_and_corner_bends https://en.wikipedia.org/wiki/Electromigration#Via_arrangeme...
      - kens 6y ago
        Both chips have a mixture of 45 and 90 degree bends, so it's nothing that obvious. About 98% of the paths are the same and then there are these changes with no discernible pattern.
        egsmi 6y ago
        In the suspected auto layout sections does it follow a modern standard cell convention?
nickff 6y ago
“Chip” is actually a term of art in the industry, used to describe ‘single passives’ (such as resistors and capacitors) in small SMD packages. There are machines called “chip shooters” which are designed to place those ‘chips’. Using the term “chip” to describe integrated circuits is amateurish.
- kryptiskt 6y ago
  Tell that to the IEEE https://www.hotchips.org https://www.hotchips.org
- Treblemaker 6y ago
  Perhaps so in the context of PCB assembly. In the semiconductor industry we still call them chips. So do Micron Semiconductor [1], TSMC [2] and Intel [3] [1] https://www.micron.com/foundation/semiconductors https://www.micron.com/foundation/semiconductors [2] https://www.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm https://www.tsmc.com/english/dedicatedFoundry/technology/SoI... [3] (pdf) http://download.intel.com/pressroom/kits/chipmaking/Making_of_a_Chip.pdf http://download.intel.com/pressroom/kits/chipmaking/Making_o...
  - pwg 6y ago
    And the usage goes back to at least August 1975 (likely earlier): http://archive.6502.org/datasheets/mos_6501-6505_mpu_preliminary_aug_1975.pdf http://archive.6502.org/datasheets/mos_6501-6505_mpu_prelimi... "but including an on-chip clock ... in addition to the on-chip clock"
    - kps 6y ago
      Two unrelated papers in AFIPS '65 use ‘chip’ in their abstracts, in the integrated circuit sense, and neither draws attention to the term. https://dl.acm.org/doi/10.1145/1463891.1464005 https://dl.acm.org/doi/10.1145/1463891.1464005 https://dl.acm.org/doi/10.1145/1463891.1463961 https://dl.acm.org/doi/10.1145/1463891.1463961
- dboreham 6y ago
dang 6y ago
Fixed now. Thanks!

kens 6y ago

I was wondering why the title ended up so bizarre. In any case, I'm the author if anyone has questions on the 8086 internals.

allenrb 6y ago
Hi Ken, love pretty much everything you write. Was wondering, is it correct to assume that all of the 8086 would have been laid out entirely by hand? Certainly special blocks like these charge pumps must have been, but was there any sort of design automation for things like the recently discussed register file?
- pjc50 6y ago
  Followup question: when did we start describing these things with GDSII files (was there a GDSI?) rather than giant sheets of acetate?
- kens 6y ago
  I think it was a mixture of hand layout and automated layout. There are a lot of places that do strange things to squeeze out every last bit of space, and I think this optimization was done by machine. For instance, long signal traces have a lot of twists and turns to be as close together as possible while avoiding obstacles and satisfying the design rules. Sometimes these signals do strange things like switching from poly wires to metal wires and back just so they can be a bit closer. These micro-optimizations don't seem like ones a human would make. Another thing I've noticed is between two revisions of the chip that have identical layout except for a few traces. On one chip a trace will have a jog that's two 90-degree turns. On the other chip, the same trace will have 45 degree bends. So the two traces are identical except for this short segment. I assume that the automated layout algorithm changed slightly, resulting in this change.
  - userbinator 6y ago
    On one chip a trace will have a jog that's two 90-degree turns. On the other chip, the same trace will have 45 degree bends. If the 45 degree one is the newer version, that might be a DFM optimisation - there is common folklore around PCB design that 90 or acute angles can cause various problems, with some hint of truth to it, but I suspect there are similar constraints in photolithography. If the sharp corner was causing yield losses, a newer revision would definitely address that.
    - dboreham 6y ago
      Electrons fly off as they try to take the 90 bend.
      - amelius 6y ago
        Electrons in a typical circuit have a drift velocity that is very low (order of millimeters per hour). Of course, the electrons individually are very fast, but they are also almost as fast when there is no voltage applied.
      - userbinator 6y ago
        There is a bit of truth to that --- sharp corners are more prone to electromigration: https://en.wikipedia.org/wiki/Electromigration#Via_arrangements_and_corner_bends https://en.wikipedia.org/wiki/Electromigration#Via_arrangeme...
    - kens 6y ago
      Both chips have a mixture of 45 and 90 degree bends, so it's nothing that obvious. About 98% of the paths are the same and then there are these changes with no discernible pattern.
      - egsmi 6y ago
        In the suspected auto layout sections does it follow a modern standard cell convention?

nickff 6y ago

“Chip” is actually a term of art in the industry, used to describe ‘single passives’ (such as resistors and capacitors) in small SMD packages. There are machines called “chip shooters” which are designed to place those ‘chips’. Using the term “chip” to describe integrated circuits is amateurish.

kryptiskt 6y ago
Tell that to the IEEE https://www.hotchips.org https://www.hotchips.org
Treblemaker 6y ago
Perhaps so in the context of PCB assembly. In the semiconductor industry we still call them chips. So do Micron Semiconductor [1], TSMC [2] and Intel [3] [1] https://www.micron.com/foundation/semiconductors https://www.micron.com/foundation/semiconductors [2] https://www.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm https://www.tsmc.com/english/dedicatedFoundry/technology/SoI... [3] (pdf) http://download.intel.com/pressroom/kits/chipmaking/Making_of_a_Chip.pdf http://download.intel.com/pressroom/kits/chipmaking/Making_o...
- pwg 6y ago
  And the usage goes back to at least August 1975 (likely earlier): http://archive.6502.org/datasheets/mos_6501-6505_mpu_preliminary_aug_1975.pdf http://archive.6502.org/datasheets/mos_6501-6505_mpu_prelimi... "but including an on-chip clock ... in addition to the on-chip clock"
  - kps 6y ago
    Two unrelated papers in AFIPS '65 use ‘chip’ in their abstracts, in the integrated circuit sense, and neither draws attention to the term. https://dl.acm.org/doi/10.1145/1463891.1464005 https://dl.acm.org/doi/10.1145/1463891.1464005 https://dl.acm.org/doi/10.1145/1463891.1463961 https://dl.acm.org/doi/10.1145/1463891.1463961
dboreham 6y ago

dang 6y ago

Fixed now. Thanks!