« The big change here is that the command and address bus is being shrunk and partitioned, with the pins being reallocated to the data bus for the second memory

« The big change here is that the command and address bus is being shrunk and partitioned, with the pins being reallocated to the data bus for the second memory channel. Instead of a single 24-bit CA bus, DDR5 will have two 7-bit CA busses, one for each channel » If there are two 32-bit data busses rather than one 64-bit bus, arithmetic suggests they shouldn't need to find extra pins from somewhere. So maybe the rationale for shrinking the CA busses (to 7 rather than 12) is something different?