4 ms·

The JOP served me well for years of research work, but only little commercial success. This project is kind of stalled. JOP’s strength was worst-case execution

The JOP served me well for years of research work, but only little commercial success. This project is kind of stalled. JOP’s strength was worst-case execution time, not average case speed. No Java processor beats JIT on a modern Intel processor.

FullyFunctional 6y ago
JOP is pretty neat and a good reminder that FPGAs enables us to make unconventional machines. Another impressive one is J16 which is an amazingly small FORTH machine. I'm surprised that I haven't found a Lisp machine, but at least there's Reduceron for lazy function languages (complete with hardware GC).
- MaxBarraclough 6y ago
  > Another impressive one is J16 which is an amazingly small FORTH machine Did you mean the J1? https://www.excamera.com/sphinx/fpga-j1.html https://www.excamera.com/sphinx/fpga-j1.html
  - deleted 6y ago
    [deleted]
  - FullyFunctional 6y ago
    yes, thanks
- jonjacky 6y ago
  There have been a few Lisp processors made with FPGAs: http://www.aviduratas.de/lisp/lispmfpga/ http://www.aviduratas.de/lisp/lispmfpga/ https://opencores.org/projects/igor https://opencores.org/projects/igor also https://www.flickr.com/photos/kaitorge/sets/72157609445719327/show/ https://www.flickr.com/photos/kaitorge/sets/7215760944571932... https://www.mail-archive.com/picolisp@software-lab.de/msg04823.html https://www.mail-archive.com/picolisp@software-lab.de/msg048... also https://www.mail-archive.com/picolisp@software-lab.de/msg04837.html https://www.mail-archive.com/picolisp@software-lab.de/msg048...
GregarianChild 6y ago
Do you think it would be possible to have hardware acceleration for JIT compilation that could beat a pure software JIT (ignoring special purpose domains like real-time)? If so, how?
- buildbot 6y ago
  I don’t see any reason why you couldn’t code a JIT to run on an FPGA, though it might not be faster than 3ghz of the excellent branch prediction/Instruction level parallelism in a modern x86 processor.
  - GregarianChild 6y ago
    Faster has two important dimensions in JIT compilers: faster compilation and (more important): faster resulting executables. Both are related, in that the quality of optimisation is traded-off against how long the optimiser can run.
- jecel 6y ago
  https://riscv.org/wp-content/uploads/2017/05/Wed1545-HybridDBT-Rokicki.pdf https://riscv.org/wp-content/uploads/2017/05/Wed1545-HybridD... This presentation uses a NIOS II processor to translate RISC-V instructions to a VLIW. Then it replaces the three most time critical parts of the software with hardware blocks.
sitkack 6y ago
I remember following and very much enjoying the development of your project years ago. I admire your project for its daringness to cross so many boundaries. Are you still working with FPGAs? Have you played with the Open Source tooling symbiflow? If you re-designed JOP what would you change? If you could change the FPGA fabric to better support a processor like JOP, what would it be? https://hackaday.com/tag/symbiflow/ https://hackaday.com/tag/symbiflow/ edit, I see have continued publishing, https://www.jopdesign.com/publications.html https://www.jopdesign.com/publications.html and I think many of my questions are answered there. Specifically, https://www.jopdesign.com/doc/icap-ctrl.pdf https://www.jopdesign.com/doc/icap-ctrl.pdf
- schoeberl 6y ago
  So many questions ;-) Yes, I have still quite some fun with FPGAs. I am interested into open source tooling, e.g., using Chisel and want to look into yosys. Redesign of JOP: 1. switch from VHDL to Chisel, 2. change the cache to be able to read one bytecode per clock cycle, 3. maybe some bytecode fusion (executing more than one per clock cycle), 4. time-predictable branch prediction. Mmh, looks like there is some open work ;-)

FullyFunctional 6y ago

JOP is pretty neat and a good reminder that FPGAs enables us to make unconventional machines. Another impressive one is J16 which is an amazingly small FORTH machine. I'm surprised that I haven't found a Lisp machine, but at least there's Reduceron for lazy function languages (complete with hardware GC).

MaxBarraclough 6y ago
> Another impressive one is J16 which is an amazingly small FORTH machine Did you mean the J1? https://www.excamera.com/sphinx/fpga-j1.html https://www.excamera.com/sphinx/fpga-j1.html
- deleted 6y ago
  [deleted]
- FullyFunctional 6y ago
  yes, thanks
jonjacky 6y ago
There have been a few Lisp processors made with FPGAs: http://www.aviduratas.de/lisp/lispmfpga/ http://www.aviduratas.de/lisp/lispmfpga/ https://opencores.org/projects/igor https://opencores.org/projects/igor also https://www.flickr.com/photos/kaitorge/sets/72157609445719327/show/ https://www.flickr.com/photos/kaitorge/sets/7215760944571932... https://www.mail-archive.com/picolisp@software-lab.de/msg04823.html https://www.mail-archive.com/picolisp@software-lab.de/msg048... also https://www.mail-archive.com/picolisp@software-lab.de/msg04837.html https://www.mail-archive.com/picolisp@software-lab.de/msg048...

GregarianChild 6y ago

Do you think it would be possible to have hardware acceleration for JIT compilation that could beat a pure software JIT (ignoring special purpose domains like real-time)? If so, how?

buildbot 6y ago
I don’t see any reason why you couldn’t code a JIT to run on an FPGA, though it might not be faster than 3ghz of the excellent branch prediction/Instruction level parallelism in a modern x86 processor.
- GregarianChild 6y ago
  Faster has two important dimensions in JIT compilers: faster compilation and (more important): faster resulting executables. Both are related, in that the quality of optimisation is traded-off against how long the optimiser can run.
jecel 6y ago
https://riscv.org/wp-content/uploads/2017/05/Wed1545-HybridDBT-Rokicki.pdf https://riscv.org/wp-content/uploads/2017/05/Wed1545-HybridD... This presentation uses a NIOS II processor to translate RISC-V instructions to a VLIW. Then it replaces the three most time critical parts of the software with hardware blocks.

sitkack 6y ago

I remember following and very much enjoying the development of your project years ago. I admire your project for its daringness to cross so many boundaries. Are you still working with FPGAs? Have you played with the Open Source tooling symbiflow? If you re-designed JOP what would you change? If you could change the FPGA fabric to better support a processor like JOP, what would it be? https://hackaday.com/tag/symbiflow/ https://hackaday.com/tag/symbiflow/ edit, I see have continued publishing, https://www.jopdesign.com/publications.html https://www.jopdesign.com/publications.html and I think many of my questions are answered there. Specifically, https://www.jopdesign.com/doc/icap-ctrl.pdf https://www.jopdesign.com/doc/icap-ctrl.pdf

schoeberl 6y ago
So many questions ;-) Yes, I have still quite some fun with FPGAs. I am interested into open source tooling, e.g., using Chisel and want to look into yosys. Redesign of JOP: 1. switch from VHDL to Chisel, 2. change the cache to be able to read one bytecode per clock cycle, 3. maybe some bytecode fusion (executing more than one per clock cycle), 4. time-predictable branch prediction. Mmh, looks like there is some open work ;-)