4 ms·

Wow another great post! I had a question about the following passage: >"The photo above shows part of the microcode ROM. Under a microscope, the contents of t

Wow another great post! I had a question about the following passage: >"The photo above shows part of the microcode ROM. Under a microscope, the contents of the microcode ROM are visible, and the bits can be read out, based on the presence or absence of transistors in each position. The ROM consists of 512 micro-instructions, each 21 bits wide." I was curious why 21 bits? I would have expected this would have been a multiple or instruction size or perhaps also 16 bits. Or is there really no correlation between size of an instruction and it's underlying micro-ops? One other question I had was in regards to the "Closeup of some transistors in the 8086" photo where the author states: >"The circles are connections (called vias) between the silicon layer and the metal wiring, while the small squares are connections between the silicon layer and the polysilicon." Vias are alway vertical correct? So are we looking at the chip from the top looking downward then? Why don't we see the metal layers then? Or do the metal wires themselves constitute the metal layer?

marcosdumay 6y ago
You create the microcode exactly as wide as necessary to control all the hardware. Any extra bit would double the size of that storage area, and it's already one of the largest things on the chip.
- Taniwha 6y ago
  you're thinking of address bits - going from 21-bits to 22-bits of microcode increases the area by 1/21th
  - deleted 6y ago
    [deleted]
  - marcosdumay 6y ago
    Oh, that's right. It increases linearly with the size of the CPU instruction words in a dimension and the size of the microcode instruction words on the other dimension. The entire exponential addressing space is not used, since there is an overall structure to both instruction sets.
jecel 6y ago
You can divide a processor into two blocks connected to each other: the control and the data path. A 1970s book illustrated this as a puppet controlled by strings, with the puppet being the data path and the hands at the other end of the strings as the control. How many strings do you need? The data path has a bunch of registers, things like an ALU, busses and multiplexers. You need a "write enable" wire for each register (or a single enable plus a small number of address bits), select signals for the multiplexers and some control bits for the ALU. 21 bits is as reasonable a number as any other. A slightly different data path might require fewer or more control signals even when used to execute the exact same instructions. The metal layer is deposited on the whole wafer, but then everything is etched away except where you want wires. So the "wires" and the "metal layer" are indeed the same thing. The vias are just little wells in the oxide beneath the metal layer. So when you deposited metal on the whole wafer some of that filled in the little well making a vertical connection between the wire and what was under the oxide.
- bogomipz 6y ago
  >"A 1970s book illustrated this as a puppet controlled by strings, with the puppet being the data path and the hands at the other end of the strings as the control. How many strings do you need?" That's a great visual. I would love to find the original text if you or anyone else remember's the title.
  - jecel 6y ago
    The version I have is a Portuguese translation, but a 1982 edition in English is: https://www.amazon.com/exec/obidos/ASIN/0960786406/acmorg-20 https://www.amazon.com/exec/obidos/ASIN/0960786406/acmorg-20 "Computer Design" by Glen. G. Langdon https://archive.org/details/computerdesign00lang https://archive.org/details/computerdesign00lang
kens 6y ago
Why 21 bits? The first factor is there is absolutely no need for an instruction to be 8, 16, or 32 bits. Modern processors use these sizes to be compatible with the 8-bit byte, but older processors used whatever word size was convenient: 12 bits, 13 bits, 17 bits, 27 bits, or pretty much anything. The second factor is that (as you suspect) there isn't any connection between the size of the machine instructions and the size of the micro-instructions. Finally, the width of a micro-instruction depends on how much you want to control at once. You can have a micro-instruction that is 100 bits wide, letting the processor do different things in parallel (e.g. IBM 360 mainframe), or a very short micro-instruction that doesn't do very much. The choice of 21 bits is enough for each micro-instruction to do two things (a data transfer and an operation). Having a 100-bit wide micro-instruction would improve performance but make the ROM too large, so it is a tradeoff. (Lookup vertical and horizontal microcode for more information.) For your second question, the photos are all looking downward onto the chip through a microscope. In the first die photo, you're looking at the metal layer. But in the closeup photo, I've removed the metal and polysilicon layers with acid, so you see the silicon layer. It's tricky to show how all the overlapping layers are connected, so I didn't do that in this post. But I have another post that shows how the layers work together in the 6502: http://www.righto.com/2013/01/a-small-part-of-6502-chip-explained.html http://www.righto.com/2013/01/a-small-part-of-6502-chip-expl...
- bogomipz 6y ago
  >"Modern processors use these sizes to be compatible with the 8-bit byte, but older processors used whatever word size was convenient: 12 bits, 13 bits, 17 bits, 27 bits, or pretty much anything." Indeed. I guess it's easy to forget that processor in the 1950s up until 1970's or really before the microprocessor era were all over the map with word sizes. Thanks for the clarification of the die photo. That makes sense. By the way I really enjoy these posts and the discussions. Keep up the great work. Cheers.
pwg 6y ago
> I was curious why 21 bits? I would have expected this would have been a multiple or instruction size or perhaps also 16 bits. Or is there really no correlation between size of an instruction and it's underlying micro-ops? There is no direct correlation between the external instruction size and the internal microcode width. The microcode ROM only needs enough bit width to generate all the control signals necessary to drive the hardware. And when laying out a mask ROM on an IC, the designer can make the ROM any bit-unit width they need for the task at hand. In this case, the 8086 only needed 21 bits to drive the hardware and so the layout was a 21 bit wide ROM.
kiwidrew 6y ago
> I was curious why 21 bits? I would have expected this would have been a multiple or instruction size or perhaps also 16 bits. Or is there really no correlation between size of an instruction and it's underlying micro-ops? From the US4449184 patent [1], the microcode format was: 5 bits - S (data source) 5 bits - D (data destination) 2 bits - TYP (microinstruction type, e.g. 1 for an ALU op) 5 bits - A (opcode) 3 bits - B (varies by instruction type) 1 bits - F (whether to update the status flags) In the second figure of the patent, you can clearly see the source/dest controls (each 5 bits) leaving the microcode ("STG 2 ARRAY") and labelled "S-BUS" and "D-BUS". There's another 5 bits (labelled "A-BUS") going to the ALU opcode decoder, 2 bits going to the "CR INC" regsiter (for jumping/branching within the microcode) and a couple of other miscellaneous bits that seem to influence the decoding of further instruction bytes. So why 21 bits? That's exactly how many bits were needed to encode all of the various microinstruction fields, no more and no less. Since the ROM is internal to the CPU, there's no need to fit the instructions into an integral number of bytes. [1] https://patents.google.com/patent/US4449184 https://patents.google.com/patent/US4449184
- kens 6y ago
  The thing that puzzles me is there are 6 values for TYP (patent col 24 line 63) but only two bits instead of three. So they must be doing something tricky like borrowing a bit from A or B. Also, kiwidrew, if you're examining this closely, the 2 bits go from CR INC to the MUX, not to CR INC. What they are doing is generating a microcode start address from the instruction, and assigning 16 micro-instructions to that instruction by default. CR INC is a counter that steps through these micro-instructions. The idea is that most instruction (< 16 micro-instructions) won't need to do any jumps. A tricky part is that 2 bits of CR INC are part of the microcode row address, while the other 2 bits select 1/4 of the row. In other words, there are four 21-bit micro-instructions in each physical 84-bit row, so the ROM array isn't excessively tall and skinny.
  - kiwidrew 6y ago
    Ah ha, thanks for explaining CR INC, that makes sense now. I have only been looking at the diagrams in the patent. The patent does enumerate (col 25 line 15) the TYP values: 0, 1, 4, 5, and 6. (The microcode listings also sometimes use a value of 7 for TYP.) So this would suggest that types 0 [conditional jump] and 1 [ALU operation] use a full 5-bit A field (to set the ALU opcode) while types 4-7 use a different format for the A and B fields. The MSB of TYP would select between the two formats, and this would explain the absence of a type 2 or type 3 instruction.

marcosdumay 6y ago

You create the microcode exactly as wide as necessary to control all the hardware. Any extra bit would double the size of that storage area, and it's already one of the largest things on the chip.

Taniwha 6y ago
you're thinking of address bits - going from 21-bits to 22-bits of microcode increases the area by 1/21th
- deleted 6y ago
  [deleted]
- marcosdumay 6y ago
  Oh, that's right. It increases linearly with the size of the CPU instruction words in a dimension and the size of the microcode instruction words on the other dimension. The entire exponential addressing space is not used, since there is an overall structure to both instruction sets.

jecel 6y ago

You can divide a processor into two blocks connected to each other: the control and the data path. A 1970s book illustrated this as a puppet controlled by strings, with the puppet being the data path and the hands at the other end of the strings as the control. How many strings do you need? The data path has a bunch of registers, things like an ALU, busses and multiplexers. You need a "write enable" wire for each register (or a single enable plus a small number of address bits), select signals for the multiplexers and some control bits for the ALU. 21 bits is as reasonable a number as any other. A slightly different data path might require fewer or more control signals even when used to execute the exact same instructions. The metal layer is deposited on the whole wafer, but then everything is etched away except where you want wires. So the "wires" and the "metal layer" are indeed the same thing. The vias are just little wells in the oxide beneath the metal layer. So when you deposited metal on the whole wafer some of that filled in the little well making a vertical connection between the wire and what was under the oxide.

bogomipz 6y ago
>"A 1970s book illustrated this as a puppet controlled by strings, with the puppet being the data path and the hands at the other end of the strings as the control. How many strings do you need?" That's a great visual. I would love to find the original text if you or anyone else remember's the title.
- jecel 6y ago
  The version I have is a Portuguese translation, but a 1982 edition in English is: https://www.amazon.com/exec/obidos/ASIN/0960786406/acmorg-20 https://www.amazon.com/exec/obidos/ASIN/0960786406/acmorg-20 "Computer Design" by Glen. G. Langdon https://archive.org/details/computerdesign00lang https://archive.org/details/computerdesign00lang

kens 6y ago

Why 21 bits? The first factor is there is absolutely no need for an instruction to be 8, 16, or 32 bits. Modern processors use these sizes to be compatible with the 8-bit byte, but older processors used whatever word size was convenient: 12 bits, 13 bits, 17 bits, 27 bits, or pretty much anything. The second factor is that (as you suspect) there isn't any connection between the size of the machine instructions and the size of the micro-instructions. Finally, the width of a micro-instruction depends on how much you want to control at once. You can have a micro-instruction that is 100 bits wide, letting the processor do different things in parallel (e.g. IBM 360 mainframe), or a very short micro-instruction that doesn't do very much. The choice of 21 bits is enough for each micro-instruction to do two things (a data transfer and an operation). Having a 100-bit wide micro-instruction would improve performance but make the ROM too large, so it is a tradeoff. (Lookup vertical and horizontal microcode for more information.) For your second question, the photos are all looking downward onto the chip through a microscope. In the first die photo, you're looking at the metal layer. But in the closeup photo, I've removed the metal and polysilicon layers with acid, so you see the silicon layer. It's tricky to show how all the overlapping layers are connected, so I didn't do that in this post. But I have another post that shows how the layers work together in the 6502: http://www.righto.com/2013/01/a-small-part-of-6502-chip-explained.html http://www.righto.com/2013/01/a-small-part-of-6502-chip-expl...

bogomipz 6y ago
>"Modern processors use these sizes to be compatible with the 8-bit byte, but older processors used whatever word size was convenient: 12 bits, 13 bits, 17 bits, 27 bits, or pretty much anything." Indeed. I guess it's easy to forget that processor in the 1950s up until 1970's or really before the microprocessor era were all over the map with word sizes. Thanks for the clarification of the die photo. That makes sense. By the way I really enjoy these posts and the discussions. Keep up the great work. Cheers.

pwg 6y ago

> I was curious why 21 bits? I would have expected this would have been a multiple or instruction size or perhaps also 16 bits. Or is there really no correlation between size of an instruction and it's underlying micro-ops? There is no direct correlation between the external instruction size and the internal microcode width. The microcode ROM only needs enough bit width to generate all the control signals necessary to drive the hardware. And when laying out a mask ROM on an IC, the designer can make the ROM any bit-unit width they need for the task at hand. In this case, the 8086 only needed 21 bits to drive the hardware and so the layout was a 21 bit wide ROM.

kiwidrew 6y ago

> I was curious why 21 bits? I would have expected this would have been a multiple or instruction size or perhaps also 16 bits. Or is there really no correlation between size of an instruction and it's underlying micro-ops? From the US4449184 patent [1], the microcode format was: 5 bits - S (data source) 5 bits - D (data destination) 2 bits - TYP (microinstruction type, e.g. 1 for an ALU op) 5 bits - A (opcode) 3 bits - B (varies by instruction type) 1 bits - F (whether to update the status flags) In the second figure of the patent, you can clearly see the source/dest controls (each 5 bits) leaving the microcode ("STG 2 ARRAY") and labelled "S-BUS" and "D-BUS". There's another 5 bits (labelled "A-BUS") going to the ALU opcode decoder, 2 bits going to the "CR INC" regsiter (for jumping/branching within the microcode) and a couple of other miscellaneous bits that seem to influence the decoding of further instruction bytes. So why 21 bits? That's exactly how many bits were needed to encode all of the various microinstruction fields, no more and no less. Since the ROM is internal to the CPU, there's no need to fit the instructions into an integral number of bytes. [1] https://patents.google.com/patent/US4449184 https://patents.google.com/patent/US4449184

kens 6y ago
The thing that puzzles me is there are 6 values for TYP (patent col 24 line 63) but only two bits instead of three. So they must be doing something tricky like borrowing a bit from A or B. Also, kiwidrew, if you're examining this closely, the 2 bits go from CR INC to the MUX, not to CR INC. What they are doing is generating a microcode start address from the instruction, and assigning 16 micro-instructions to that instruction by default. CR INC is a counter that steps through these micro-instructions. The idea is that most instruction (< 16 micro-instructions) won't need to do any jumps. A tricky part is that 2 bits of CR INC are part of the microcode row address, while the other 2 bits select 1/4 of the row. In other words, there are four 21-bit micro-instructions in each physical 84-bit row, so the ROM array isn't excessively tall and skinny.
- kiwidrew 6y ago
  Ah ha, thanks for explaining CR INC, that makes sense now. I have only been looking at the diagrams in the patent. The patent does enumerate (col 25 line 15) the TYP values: 0, 1, 4, 5, and 6. (The microcode listings also sometimes use a value of 7 for TYP.) So this would suggest that types 0 [conditional jump] and 1 [ALU operation] use a full 5-bit A field (to set the ALU opcode) while types 4-7 use a different format for the A and B fields. The MSB of TYP would select between the two formats, and this would explain the absence of a type 2 or type 3 instruction.