3 ms·
No need to wait, the ESP32-S2 has a RISC-V as its low-power core.
by MrBuddyCasino 6y ago
No need to wait, the ESP32-S2 has a RISC-V as its low-power core.
- sitkack 6y agoESP32-S2 has two ULP co-processors, with one based on RISCV instruction set architecture (ULP-RISCV) and the other on finite state machine (ULP-FSM). ULP-RISCV has the following features: support for IMC instruction set thirty-two 32-bit general-purpose registers 32-bit multiplier and divider support for interrupts boot by the CPU, its dedicated timer, or RTC GPIO https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf https://www.espressif.com/sites/default/files/documentation/...
- MrBuddyCasino 6y agoInteresting, wasn't aware. Is the ULP-FSM the same as the one in the original ESP32? I thought that one was programmable / Turing-complete, so not just a FSM?
- sitkack 6y agoI have never used the ULP-FSM, the new docs for ESP32-S2 are fascinating. My S2 is on its way, I don't yet have the hardware in hand.