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Frequency is no longer a good proxy for speed, what with advancements in ipc. Also, note that the amount of memory in a cray-1 is similar (within 1-2 orders of
by moonchild 7y ago
Frequency is no longer a good proxy for speed, what with advancements in ipc. Also, note that the amount of memory in a cray-1 is similar (within 1-2 orders of magnitude) to the amount of cache in a modern cpu.
- wahern 7y agoFrequency is still very much a good proxy for speed, especially in the context of a chip which has the same deep pipelines and sophisticated scheduling that made "frequency is no longer a good proxy for speed" a popular retort. The benefits of improved IPC are dwarfed by the frequency gains as compared to those older chips.
- moonchild 7y agoNot really. Straight FLOPS might increase pretty-much linearly, but that's not representative of a typical workload. Cache latency (as measured in clock cycles) and size in a modern core is comparable to memory in an older CPU, as I mention in the parent. But speculative execution means you can effectively use the 'slower' medium (memory) for intermediate computation.
- corysama 7y agohttps://unfoxnews.com/clocking-a-6502-to-15ghz/ https://unfoxnews.com/clocking-a-6502-to-15ghz/ tldr: 6502 is very similar to 8086 and doing a binary translation is fairly straightforward. But, it turns out that many instructions that took multiple cycles on the 6502 now execute in a single cycle on x64 and pipeline deeply with other ops. So, the effective performance of a 4Ghz x64 resembles that of a 15Ghz 6052.
- moonchild 7y agoTo clarify, the problem is not 'clocks give X% improvement to performance, but architectural improvements give Y%, and Y is bigger than you give it credit for.' The problem is that CPU performance is not practical to reason about for humans. Hasn't been and probably won't ever be until/unless computers get massively rearchitectured. The speed-of-light limit means that 'fast' memory (accessible within a couple of clock cycles) will always be limited, and 'big' memory (gigabytes-terabytes size) will always be at least 100 cycles delayed. This in turn means that the cpu architecture must be asynchronous, which means it does not have consistent or intuitive performance characteristics.