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I assume that all modern CPUs are CISC-ish opcodes running in microcode on a RISC-ish core, and it’s been a few decades since those were useful labels.

by ken 6y ago

zozbot234 6y ago
There's nothing much that's CISC-like about ARM, MIPS or RISC-V. Even many μC architectures are closer to "RISC" than "CISC", though there's at least some room for exceptions there.
- yjftsjthsd-h 6y ago
  > There's nothing much that's CISC-like about ARM, I struggle to think that ARM can really be called reduced-instruction after neon or so.
  - zozbot234 6y ago
    Why? NEON operates on registers, so the load-store principle is still fully in effect. And it maps directly to special-purpose hardware.
    - arnd 6y ago
      32-bit Arm has some features that make it less RISC-like than others: - Predication as a major architectural feature -- every instruction can be conditionally executed - Complex load-store instructions: ldm/stm can operate on a large set of registers in a single instruction, including performing a branch by loading into the instruction pointer - 16-bit Thumb instruction format (also optionally present in RISC-V and newer MIPS) 64-bit Arm mostly drops all of the above and is basically a traditional RISC implementation.
  - glangdale 6y ago
    RISC has never been about reduced number of instructions, but their complexity. A SIMD extension built around load/store architecture is quite compatible with the principles of RISC, despite the fact that such an extension might have very numerous instructions.
    - yjftsjthsd-h 6y ago
      Well, I learned something today:) I'd always assumed that RISC meant a reduced number of instructions, but that's clearly not the case. Wikipedia phrases it as, > The term "reduced" in that phrase was intended to describe the fact that the amount of work any single instruction accomplishes is reduced—at most a single data memory cycle—compared to the "complex instructions" of CISC CPUs that may require dozens of data memory cycles in order to execute a single instruction.[23] In particular, RISC processors typically have separate instructions for I/O and data processing. So yeah, if SIMD instructions can execute in a single cycle (or maybe even a small number), then it still counts.
fulafel 6y ago
RISCs still largely operate on the architected instructions in the pipelines. It's also a thing to fuse smaller operations into macro-ops in many microarchitectures. All high performance chips avoid running microcode, it's reserved for eg emulating seldom used legacy instructions. Microcoded CPUs (where all instuctions are implemented with microcode) were a 80s/90s thing.

I assume that all modern CPUs are CISC-ish opcodes running in microcode on a RISC-ish core, and it’s been a few decades since those were useful labels.

by ken 6y ago

I assume that all modern CPUs are CISC-ish opcodes running in microcode on a RISC-ish core, and it’s been a few decades since those were useful labels.

zozbot234 6y ago

There's nothing much that's CISC-like about ARM, MIPS or RISC-V. Even many μC architectures are closer to "RISC" than "CISC", though there's at least some room for exceptions there.

yjftsjthsd-h 6y ago
> There's nothing much that's CISC-like about ARM, I struggle to think that ARM can really be called reduced-instruction after neon or so.
- zozbot234 6y ago
  Why? NEON operates on registers, so the load-store principle is still fully in effect. And it maps directly to special-purpose hardware.
  - arnd 6y ago
    32-bit Arm has some features that make it less RISC-like than others: - Predication as a major architectural feature -- every instruction can be conditionally executed - Complex load-store instructions: ldm/stm can operate on a large set of registers in a single instruction, including performing a branch by loading into the instruction pointer - 16-bit Thumb instruction format (also optionally present in RISC-V and newer MIPS) 64-bit Arm mostly drops all of the above and is basically a traditional RISC implementation.
- glangdale 6y ago
  RISC has never been about reduced number of instructions, but their complexity. A SIMD extension built around load/store architecture is quite compatible with the principles of RISC, despite the fact that such an extension might have very numerous instructions.
  - yjftsjthsd-h 6y ago
    Well, I learned something today:) I'd always assumed that RISC meant a reduced number of instructions, but that's clearly not the case. Wikipedia phrases it as, > The term "reduced" in that phrase was intended to describe the fact that the amount of work any single instruction accomplishes is reduced—at most a single data memory cycle—compared to the "complex instructions" of CISC CPUs that may require dozens of data memory cycles in order to execute a single instruction.[23] In particular, RISC processors typically have separate instructions for I/O and data processing. So yeah, if SIMD instructions can execute in a single cycle (or maybe even a small number), then it still counts.

fulafel 6y ago

RISCs still largely operate on the architected instructions in the pipelines. It's also a thing to fuse smaller operations into macro-ops in many microarchitectures. All high performance chips avoid running microcode, it's reserved for eg emulating seldom used legacy instructions. Microcoded CPUs (where all instuctions are implemented with microcode) were a 80s/90s thing.