3 ms·
I'm not sure with cache aliasing you'd be guaranteed that it would stay all in L3.
by bgirard 7y ago
I'm not sure with cache aliasing you'd be guaranteed that it would stay all in L3.
- com2kid 7y agoIt's have to be a special setup for sure, a board with no memory even hanging off of it. In theory all you'd need is some tight integration with the NIC (or a few of em!) and tiny driver that knows how to DMA to the NIC. Larger problem of course is that L3 isn't addressable. I wonder how much money a cloud provider would have to pony up to AMD to get an exception to that? :) A huge # of workloads would fit in 16MB with no storage hanging off. Heck I think every microservice I've ever written could manage that. There have been some efforts of late to make a cloud first OS, honestly once you remove everything except for "talk to network controller" and "parse JSON", well so long as you don't mind writing in a language that isn't JS, a few MB is plenty for lots of workloads.
- gpderetta 7y agoApparently there are ways to treat the cache as a static scratch pad. It is used by BIOSes during early startup, but I'm not sure whether the magic incantations are publicly known. It is second hand knowledge though, so it might just be folklore.
- Dylan16807 7y agoIf you allocate one big block it would fit even in a 1-way cache. Modern chips appear to have 16-way L3, so you'd have to be trying to spill.