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Why the EAX register of x86 is called that
- based2 7y agohttps://www.reddit.com/r/programming/comments/fm2xb9/heres_why_the_eax_register_of_x86_is_called_like/ https://www.reddit.com/r/programming/comments/fm2xb9/heres_w...
- jchw 7y agoI was wondering if it was going to cover RAX/amd64, and it does. Nothing terribly new here but it’s a nice dive into an interesting microcosm of intel architecture. I do somewhat wish AMD managed to get R0-R7 as the standard, though :p oh well.
- remcob 7y agoThe R0-R7 naming is pretty widely supported. For example by LLVM's assembler, so you can use it in Rust or C(++) inline assembly.
- billfruit 7y agoMore interestingly why are FS and GS registers called so?
- Narishma 7y agoMaybe because they come after DS and ES.
- rzzzt 7y agoCS, DS and ES also have letters in alphabetical order, yet they are treated as acronyms. Wondering why is there no meaning (even if fabricated) attached to FS and GS?
- rwmj 7y agoNot really sure what your question means, but originally CS for "code segment", DS for "data segment" and SS for "stack segment" had distinct use cases. They weren't general purpose segment registers at all. ES was an "extra" data segment register. When FS and GS were added later the alphabetical ordering of CS, DS, ES, FS, GS was natural (with SS still being the odd one out).
- gmueckl 7y agoEven in 32 bit mode, x86 uses segmented menory access and CS, DS and SS retain their roles as default segments for code, data and stack memory accesses. IIRC, all the segment registers are special because the CPU caches the corresponding segment table entry transparently in the background. The table entries are fairly complex.
- iforgotpassword 7y agoThat's how we got virtualization on x86. When AMD killed segmentation in AMD64, VMware et al cried out loud. AMD reintroduced segmentation after that as a stop-gap solution, but then we got VTx and SVM which are a much better solution anyways.
- rzzzt 7y agoPrecisely what you wrote: CS is "Code Segment", DS is "Data Segment", ES is "Extra Segment" (even here it feels a bit manufactured), but FS and GS lack any semi-reasonable expansion.
- jpxw 7y agoFrom reddit: “This is basically the report_final_FINAL2.docx of register names.”
- read_if_gay_ 7y agox86 in its entirety is report_final_FINAL2.docx
- nitrogen 7y agoWhere does that filename meme come from?
- pas 7y agoPeople's "Downloads" folder being full of New folder", "New folder (1)", all of them being full of similarly named documents. Also anyone not using proper version control (business folks, designers, scientists, students) usually has a bunch of files all over the place with every kind of inconsistent names for a bunch of versions.
- psychoslave 7y agoI can use proper version control for code, but when it comes to office products, I use an ISO date to prefix my "versions" of files. This is really an integration of proper version control within the workflow. I don't find it appropriate to blame the user when they are so misguided. Don't get me wrong, an ISO date prefix is nothing close to perfect for version control, but it: - works anywhere you are asked to name a sequence of things - tacitly communicates well the naming scheme so your colleagues can get it and possibly even start to imitate it - give a clear time referral - isn't sensible to system time-stamp, so this keep the chronology even when file are touched or copied elsewhere with a different time-stamp - spontaneously generate a chronologically ordered result of versions when their are displayed in list Once again, this is not my favorite way to organize things. But from a practical point of view, it often comes as the less worst solution you can run seamlessly.
- 7y ago
- jbverschoor 7y agoHmm I guess I'm getting old. ehhh senior
- kazinator 7y agoA is the A register, first letter of the alphabet. Under 16 bits, it has a high and low part, AL and AH. The 16 bit whole got called AX, because X gets used a lot as a wild card. EAX is extended (to 32 bits) AX.
- iforgotpassword 7y agoThen you could have kept calling it A.
- danmg 7y agoNo. because you still have the opcodes that operate on just 64/32/16/8 bits of the register.
- thaumasiotes 7y agoAren't those AL and AH? When we rename A to AL, why do we need to permanently retire the term "A"? The L in AL stands for "low"; what does the A stand for?
- jonsen 7y agoAccumulator.
- thaumasiotes 7y agoYou're missing my point. AL is the "L"ow bits of the "A" register. AH is the "H"igh bits of the "A" register. The whole thing, low plus high, is the "A" register. We can tell that by the names AL and AH.
- saagarjha 7y ago> The whole thing, low plus high, is the "A" register. Well, it's the "AX" register.
- 7y ago
- maayank 7y agoI LOVE this kind of technical computer history! Anyone knows of other recommended resources?
- woadwarrior01 7y agoIf you’re visiting the Bay Area, be sure to visit the Computer History Museum in Mountain View. It’s the Mecca of computing history. Also, for early internet history, I’d recommend Katie Hafner’s book: Where Wizards Stay Up Late.
- maayank 7y agoI did and I loved every moment of it :) Also in meatspace, enjoyed Bletchley Park in the UK. Re: books, I liked Robert X. Cringley's Accidental Empires, but it covers only until 91 (or 93 if IIRC for the 2nd edition) of the PC industry and not really technical. edit: also, of course: https://devblogs.microsoft.com/oldnewthing/ https://devblogs.microsoft.com/oldnewthing/
- Y_Y 7y agoThe Bletchley Park museum is about ten times better and has lots of running computers, knowledgeable staff, and stuff to play with.
- coldpie 7y agoIt's more electrical/silicon engineering than technical history, but I absolutely love this article: "The 6502 CPU's overflow flag explained at the silicon level" by Ken Shirriff, http://www.righto.com/2013/01/a-small-part-of-6502-chip-explained.html http://www.righto.com/2013/01/a-small-part-of-6502-chip-expl...
- JoeAltmaier 7y agoThe iAPX 432 was long after the 8086, not before. And the 80286 predated the 80386 as a 32-bit processor, so the 80286 was Intel's first 32-bit offering. It was still segmented, missing the paging hardware. I helped write an operating system for it. Short-lived.
- intc 7y ago20286 was a 16 bit CPU. But it was the first one to support "protected mode".
- JoeAltmaier 7y agoI remember, we called that 'imaginary mode' since it required substantial rewriting of code and few made the attempt.
- ch_123 7y agoThe iAPX 432 project started in 1975, but took many years to deliver anything. The 8086 was indeed intended as a stop gap while the ‘432 was under development. The 80286 by most definitions was a 16-bit CPU, having a 16-bit data bus, 16-bit general purpose registers and 16-bit segments. It did have a 24-bit address space though, up from the 20 bits of the 8086. EDIT: Even Intel called the 286 a 16-bit CPU, see the Preface of http://bitsavers.trailing-edge.com/components/intel/80286/210498-005_80286_and_80287_Programmers_Reference_Manual_1987.pdf http://bitsavers.trailing-edge.com/components/intel/80286/21...
- JoeAltmaier 7y agoOh of course! Thanks. The 24-bit address space changed operating system designs to use a LONG to store physical memory addresses, which I guess confused my memory of the whole thing. It had 'real mode' which was the ordinary 8086 addressing mode (capable of 20-bit addressing to 1MB) and 'protected mode' which we called 'imaginary mode' since nobody used it.
- CalChris 7y ago> The iAPX 432 was long after the 8086, not before. That's why the article said their flagship processor iAPX 432 is delayed. The 432 started development in 1975 (!) but wasn't shipped until 1981. https://en.wikipedia.org/wiki/Intel_iAPX_432#Description https://en.wikipedia.org/wiki/Intel_iAPX_432#Description
- DmitryOlshansky 7y agoE - extended, meaning from 16 to 32 bits. A - accumulator X - wildcard for both upper and lower 8-bit parts, this becomes redundant b/c of E prefix
- perl4ever 7y agoNow I want to define an architecture just like the 8008, only with each register 64-bits and only 64-bits.
- saagarjha 7y agoDefining an architecture is easy! All you have to do is write up a document with instructions and their encodings, and boom! You’ve created a new architecture. Here’s one I made earlier this year for a class I was teaching, for example: https://github.com/regular-vm/specification https://github.com/regular-vm/specification
- tenebrisalietum 7y agoThat's such a waste if you really only need something that will fit in 8 bits. Especially limited register space. Also what if I want to deal with something like screen pixels that packs nicely in 8 bit boundaries, but maybe I don't want the first 8 bits?
- amelius 7y ago> I’m afraid there’s no short answer! We’ll have to go back to 1972… No we don't ... the E stands for "extended".
- BorisTheBrave 7y agoAnd the X also stands for extended.
- Kranar 7y agoAlternatively the X is a very old assembly notation for "pair". 8-bit registers on 8080 processors could be paired together to work as a single register. Operations performed on these register pairs used the letter X. You can look here at the original 8080 reference manual: https://altairclone.com/downloads/manuals/8080%20Programmers%20Manual.pdf https://altairclone.com/downloads/manuals/8080%20Programmers... For example page 4 lists the name of instructions, INR is "increment register" while INX is "increment register pair", similar notation is used for several other instructions where the X is the register paired version of an instruction. In the case of the AX register, it likely just refers to the pair of AH and AL registers. At any rate, it's really interesting glancing over the various 8086 reference manuals. Gives me a deep sense of appreciation for how far things have come and how things have managed to build upon what are otherwise some very simple and fundamental building blocks.
- falcrist 7y ago> B, C, D, E were completely generic and interchangeable. I was under the impression that it went Accumulator Base Counter Data I'm not sure about the D or E registers, but I am sure I remember using B as the base address register for arrays, and using C as the counter register for loops and such because the others couldn't be used that way. It's been a while. Am I misremembering?
- bonzini 7y agoYes, in the Z80 BC was a sort of counter register (e.g. for LDIR or DJNZ instructions), which is perhaps why BC became CX. In the 8080 there wasn't much difference between BC and DE. The interesting part is that BX maps to HL, which explains the weird order AX/CX/DX/BX in the encoding of 8086 instructions.
- gpvos 7y agoIt's in the article. This was introduced with the 8086; in the 8008 they were still generic.
- nayuki 7y agoExcellent explanation in the article. Also note that in x86-64 mode, the low 8 bits of all registers can be accessed, namely: AL, BL, CL, DL, SIL, DIL, SPL, BPL, R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B. Previously, there was no equivalent of SIL, DIL, SPL, and BPL. https://docs.microsoft.com/en-us/windows-hardware/drivers/debugger/x64-architecture https://docs.microsoft.com/en-us/windows-hardware/drivers/de...
- hinkley 7y agoAL, BL make sense. But now I need an explanation for why they switched from L to B for R8B... Also if you could explain A-R15 that’d be super. Apparently they have learned absolutely nothing.
- therealcamino 7y agoI had the same question about the suffix letters. My uninformed guess is: 8 bits == byte == B 16 bits == word == W 32 bits == doubleword == D
- jagrsw 7y agoI believe D for doubleword is mostly Microsoft C/C++ thing, though I'm sure it appears in other places too. When it comes to the assembler syntax 32bit word, my guess would be, that 32bit words (e.g AT&T x86 syntax, m68 assemblers) are mostly indicated as l (for long). movl (at&t's x86) or mov.l (m68k). Edit: Ah.. yeah, also intel x86 asm syntax uses it, so I guess that's where the idea of using D for 32bit values originates.
- pizlonator 7y agoFor some of the L ones it’s possible to access the H part. So it’s not just a byte (B) it’s the low (L) byte and there is a high (H, just the second byte of the word) you can also get to. For the high 8 registers it isn’t like that. There is no way to get to the “high” byte.
- kens 7y agoOne thing directly connected to this history is why the x86 is little-endian. As the article explains, the 8008 was designed for the Datapoint 2200 terminal. The 8008 was intended as a compatible replacement for the existing Datapoint processor, which was built from simple TTL chips. To reduce the chip count, the Datapoint 2200 used a serial processor, which processed one bit at a time, so you had a 1-bit ALU among other things. One consequence is that you have to start with the low-order bit when doing addition, so you can handle carries. And for 16-bit values, you also have to start with the low-order byte. This forces you into a little-endian architecture. Thus, to be compatible with the Datapoint 2200, the 8008 was also made little-endian. Unfortunately, Intel was very slow creating the 8008, so Datapoint had moved on to a parallel 74181-based architecture and didn't want the 8008. Intel decided to sell the 8008 as a stand-alone product, essentially creating the microprocessor industry. As the article explains, the x86 grew out of the 8008, so x86 also inherited the little-endian architecture
- kps 7y agoSimarly, x86_64 condition codes have a parity flag because the terminal needed it.
- Vogtinator 7y agoI don't think that really forced any particular endianness. Endianness is only really a thing if there's addressable memory, which is not the case for a bit stream. Whether a system is big/little/mixed-endian was only a question of how the address lines are set for multi-byte accesses.
- tomxor 7y agoI thought that too at first, but then I found this stack-overflow answer fairly convincingly confirming the OPs claim with quotes from it's designers: https://stackoverflow.com/a/36263273 https://stackoverflow.com/a/36263273 although it's still not explicitly clear why. > Shustek: So, for example, storing numbers least significant byte first, came from the fact that this was _serial_ and you needed to process the low bits first. > Poor: You had to do it that way. You had no choice. I'm wondering if it was the bit order that mattered for compatibility with the 1-bit serial processor of the Datapoint 2200, and if that determined byte ordering of it's 16bit successor?... I don't know much about 1-bit computing, but if you think about it - to be useful, it must be capable of doing operations on arbitrary length words (within some reasonable limitation), i.e not limited to 8 bits like the 8008. So maybe this put it in a funny position: while byte endianess makes no sense and bit endianness seem to make no difference for the 8008 since it was 8bit; it did make a difference to the datapoint which was serial 1-bit and could operate through the 8bit word boundaries. To be clear what i mean, imagine how a 1-bit ALU would process 16 bits, it would want them in order like this (the bits are in logical order, not numerical order): (8bit) Little Endian: byte 0000000011111111 bit 0123456789abcdef But not like this: (8bit) Big Endian: byte 0000000011111111 bit 76543210fedcba98 I don't know if this is correct, and i'm assuming here that bit endianness must determine byte endianness in the 16bit 8086. Clarification/correction is most welcome.
- knolax 7y agoAssembly mnemonics and their cousin pin names are so excessively terse. I wish it was mandatory to expand acronyms in a dedicated field in datasheets. So often you'll find pin names like "NCE" where you're just expected to know a priori that it means "active-low Chip Enable" and it's so counterproductive.
- tenebrisalietum 7y agoAssembly mnemonics I think are terse to make it dirt simple for assemblers to read them, which themselves had to be hand-entered via hex until they became "self-hosting." Assemblers could not be on the same level as compilers. This was definitely very needed when these CPUs were new in the 70's and such. I've always liked how 6502 neatly has everything in 3 letter opcodes. But that's not scalable given modern CPU capabilities.
- userbinator 7y ago...and for humans to read and write them, because what could be a single symbol in an HLL ('+') turns into several latters ('ADD') in Asm. Some companies experimented with "symbolic Asm" which was even terser, and made it look more like an HLL.
- pizlonator 7y agoI love the x86 registers and their names and special roles. On the one hand, it’s gross that x86 still has this legacy. On the other hand, it’s a good thing that it’s possible to maintain compatibility so far back while still having such good perf. I find that aspect of modern x86 to be super impressive.
- chkaloon 7y agoInteresting how much early processor history was driven by Intel project delays.
- Tuna-Fish 7y agoIMHO the story of the iAPX432 really is the whole industry in microcosm. Intel hires the best of the best, the true cream of the crop to design them an ISA that is meant to crystallize everything that is known about ISA design into a single completely new design that discards all the broken crap of yesterday and will be futureproof for decades if not forever, and a chip to implement it. Everything is going to be great forever, but it turns out it's a bit hard to get done, so they just have the B-team whip up something quick to sell in the meantime. This something was the 8086, which gets adopted into increasingly successful products, but no matter, the new shiny thing is going to displace all of that when it finally ships. Then it does, and it actually has a hard time competing in performance with the much older stopgap product. It turns out that the team of superstars they hired was very theoretical, and built an ISA that was a dream to program against, but did not really understand what it took to build something that was going to be fast when implemented in hardware. (Also, the system was meant to be used mainly with high-level languages, and the compilers really were not there yet.) Being more expensive, much slower than the competition and with 0 market penetration, the iAPX 432 was dead on arrival in the market. Luckily, the B-team had been busy working up on another extension of the stop-gap product, the 80286, which is again a runaway success, and only partially because of backwards compatibility with the existing x86 ecosystem. It was also quite fast for it's time.
- pjmlp 7y agoIntel history is full of such missteps. Last one was dropping MPX, while everyone else is making memory tagging compulsory as means to tame C and C++ code.
- JoeAltmaier 7y agoI recall the iAPX432 came out years later than the 8086, was a 'capabilities machine' and took 500 memory cycles to execute "JMP ." e.g. jump to self, potentially the simplest possible operation.
- LifeLiverTransp 7y agoThis is by now only a emulated API-Layer, while the real chip executing instructions varys wildly from what one would expect? After all, intel realized somewhere on the way, that supporting legacy was holding them back and they should also do riscy things?
- mkchoi212 7y agoSo cool. Kinda disappointed at my hacker side of things because I never questioned why EAX register is actually named "EAX". Wondering what else I take for granted now :p
- xscott 7y agoMost people list the registers in alphabetic order, but numerically they are encoded with the B registers in the 4th place: EAX=0, ECX=1, EDX=2, EBX=3, ... If you ever find yourself writing an AMD-64 assembler, it really feels like you're digging through archaeology with all of the weird quirks you need to implement. The SSE, AVX, and AVX-512 encodings add even more levels of, "why did they do that?!?" which don't make much sense except in the context of history.
- userbinator 7y agobut numerically they are encoded with the B registers in the 4th place I've never seen an authoritative answer for that but I believe it comes from the fact that in the 16-bit addressing modes, BX is the only one of the 4 ABCD registers that can be used to address memory, and the circuitry for decoding is very slightly simpler to detect two 1 bits than one 1 and one 0 bit. The 4 other registers are, in order, SP BP SI DI. which don't make much sense except in the context of history That can be said for a lot of things...
- peter_d_sherman 7y agoExcerpt: "You might think—gee, seven is a very odd number of registers—and would be right! The registers were encoded as three bits of the instruction, so it allowed for eight combinations. The last one was for a pseudo-register called M. It stood for memory. M referred to the memory location pointed by the combination of registers H and L. H stood for high byte, while L stood for low byte of the memory address. That was the only available way to reference memory in [an] 8008."