3 ms·
Huh, interesting. I don't know a lot about the various architectures, but with instructions like that, my intuition tells me you could do some really interestin
by RealityVoid 7y ago
Huh, interesting. I don't know a lot about the various architectures, but with instructions like that, my intuition tells me you could do some really interesting stuff.
Coming from an embedded background, I'm wondering, could you not, for example, do a machine where you offload bulk memory operations to the memory controller itself? Copying memory, zeroing memory, moving memory around, all these things could happen at the memory controller level and you'd never need to put them on the actual bus. Perhaps there is something like this for some exotic architectures?
- pavlov 7y agoSomething like the 1985 Amiga blitter chip?
- rvense 7y agoI've seen obscenely complicated DMA controllers that can do that and more. Check the NXP iMX6 SDMA peripveral for instance.
- RealityVoid 7y agoIt would still put it in the bus, tho, no? I'm wondering now how these processors/MCU's handle bus access since you have so many peripherals that probably want to access it as well as the CPU acceses that need to happen. Certainly you have to have a priority settling mechanism and some way of arbitrating the resource. The CPU probably doesn't use it all the time, but if you have a pipeline, it probably uses it in the background anyway.
- joezydeco 7y agoOn ARM there's a whole series of controller blocks that sit between the CPU caches and the outside world. Start looking up the AMBA (Advanced Microcontroller Bus Architecture) and you'll see how complicated it gets: https://developer.arm.com/architectures/system-architectures/amba https://developer.arm.com/architectures/system-architectures...