9 ms·
One Instruction Set Computer
- LocalMan 7y agoMost computers have only one instructions set. It might have hundreds of instructions, but it's only one set. Perhaps you nitwits mean the "One instruction" computer?
- dang 7y agoPlease don't be a jerk on HN. We're trying for a bit better than internet default here. https://news.ycombinator.com/newsguidelines.html https://news.ycombinator.com/newsguidelines.html
- dang 7y agoA thread from 2015: https://news.ycombinator.com/item?id=9388137 https://news.ycombinator.com/item?id=9388137 2011: https://news.ycombinator.com/item?id=3046980 https://news.ycombinator.com/item?id=3046980
- legulere 7y agoSo like x86 mov? https://github.com/xoreaxeaxeax/movfuscator https://github.com/xoreaxeaxeax/movfuscator
- amelius 7y agoExcept you wouldn't actually need to store the opcode for the instruction.
- excessive 7y agox86's version of a single "instruction" is frequently a large class of opcodes. It's kind of crazy considering the assembler chooses one of the following numbers for "mov" based on the operand types, not the mnemonic: 88, 89, 8A, 8B, 8C, 8E, A0, A1, A2, A3, B0, B8, C6, C7 This also ignores all of the prefix bytes. https://www.felixcloutier.com/x86/mov https://www.felixcloutier.com/x86/mov
- mike_hock 7y agoAlso, MOV is far from only a bit copy. It's (potentially, depending on the operands), left shift, add, load, store.
- lloeki 7y agoCame in to mention that, but the crazy stuff I was thinking about is surprisingly not mentioned in the main readme. Behold: https://github.com/xoreaxeaxeax/movfuscator/blob/master/validation/doom/README.md https://github.com/xoreaxeaxeax/movfuscator/blob/master/vali... Yes, Doom running with just MOV.
- mysterydip 7y agoSemi-related, I just learned about this 1-bit microprocessor the other day: https://en.m.wikipedia.org/wiki/Motorola_MC14500B https://en.m.wikipedia.org/wiki/Motorola_MC14500B
- qubex 7y agoDaniel Hillis’ famed Connection Machine architecture (until the radically revised CM-5) featured hypercube-geometry “one-bit processors” which were really “definable logic gates”.
- jzwinck 7y agoTransport Triggered Architecture seems not only isomorphic but essentially equivalent to a conventional architecture if you notice it is effectively just relocating/packing the opcode bits into the operands. This seems to be an implementation detail of the hardware (which bits does it gather opcodes from) and not an essential difference in the ISA. Am I missing something?
- guidoism 7y agoIf you had a writable control store then yes. But most processors these days don’t expose that API.
- deleted 7y ago[deleted]
- nomorerul 7y agoIs this the era of microcomputers like we have microservices?
- jes5199 7y agothat word already means something, and it describes probably every computer you’ve used in your life. so... yes? but the era of microcomputers started in 1974
- rambojazz 7y agoEvery example under "Instruction types" looks like a combination of 2 (or more) instructions. "Do this AND do that".
- saagarjha 7y agoOf course, taken to the logical extreme we can have the "RISC OISC", which is just an instruction that interprets the operand as a fixed-width instruction for a RISC architecture ;)
- int_19h 7y agoWhether something does one or several things largely depends on your perspective. You might think of ADD as a single instruction, but it fiddles with a lot of bits... This is "one instruction" in a sense of having only a single opcode.
- cellularmitosis 7y agoI’ve just recently started looking into implementing a minimal ALU, and I’ve been having trouble finding good resources to answer the question “other than a one-instruction computer, what is the smallest number of instructions needed in a Turing-complete RISC?” I’m guessing it would be NAND, ADD, increment, and some sort of branch? NAND covers all of the bitwise ops. If you have ADD, NOT and increment, you can get SUB. If you have ADD and SUB, you can get MUL and DIV. Am I missing anything?
- excessive 7y agoI don't mean this the wrong way, but since you know one instruction is sufficient, the next smallest number is two. Maybe by RISC, you meant a small orthogonal set? Load/Store/ALU ops separated? So ADD and NAND work on registers with transfers using LOAD and STORE? Seems like you'd need a branch, unless the instruction pointer was one of your registers. Brainfuck has 8 ops, 2 of which are for input and output. It's Turing complete, and the operations are super simple, but I'm not sure it's RISC-ish. https://en.wikipedia.org/wiki/Brainfuck#Commands https://en.wikipedia.org/wiki/Brainfuck#Commands
- mypalmike 7y agoYou can build ADD and INC from NAND.
- f00zz 7y agoThis (educational) ISA has just NAND and ADD: https://user.eng.umd.edu/~blj/RiSC/RiSC-isa.pdf https://user.eng.umd.edu/~blj/RiSC/RiSC-isa.pdf
- cellularmitosis 7y agoExactly what I was looking for, thanks so much!
- zzo38computer 7y agoThis is good, although I study esoteric programming so have known a few of these things. I have also once designed a schematic for a transport triggered architecture without knowing that it was called that; I just had the same idea. (But, many people will have similar ideas, and not always know what it is called.) TOGA computer is like a presettable binary counter, NOT gate, memory, some logic for timing (so that it does not interfere with itself), and not much else. But what is not mentioned is Muxcomp, which is something I am much more interested in, and is also with only one instruction. (Although, I thought of using it as part of a user-programmable VLIW microcode.)