7 ms·

The RISC-V ISA is pretty awful for high-end designs. No competitive servers can be built with it. Plenty of people seem to have been caught up in the hype of R

The RISC-V ISA is pretty awful for high-end designs. No competitive servers can be built with it. Plenty of people seem to have been caught up in the hype of RISC-V taking over the world and doing everything, but that's never going to happen. The ISA is heavily optimized towards making very low-end devices very cheap. Like, don't think cellphone chips, think appliances. This is not a bad call, as it's the area where greenfield designs with cost advantage have the best chance to get market share. However, there is no path of extending the ISA that will make it competitive with ARM or x86 on high-end devices. The only way to do that is to design RISC-VI, that abandons most of the things that RISC-V what it is.

zozbot234 7y ago
> The RISC-V ISA is pretty awful for high-end designs. No competitive servers can be built with it. I have to dispute this. RISC-V was specifically intended to make high-end designs (i.e. out-of-order architectures, multicore, SMT etc.) not just feasible but relatively easy. It's also designed for extensibility from the ground up, which few others architectures are.
pjc50 7y ago
This argument would benefit from specific examples.
tempguy9999 7y ago
You've not justified this. I'd be very interested in understanding why you make this claim.
russler23 7y ago
That’s funny, SiFive just announced a 3-way OoO RISC-V core. A73 performance, but half the die area. Pretty awful, I guess. https://www.sifive.com/blog/incredibly-scalable-high-performance-risc-v-core-ip https://www.sifive.com/blog/incredibly-scalable-high-perform...
- rrss 7y ago
  FYI the comparison is to the A72, not A73. A72 is a mobile chip, so still not particularly relevant to tuna-fish's claim about high end servers. The raspberry pi 4 is not a high end server. > half the die area Much of this is free when comparing a 16nm design to a 7nm design. See footnote 1 in your link. EDIT: I was curious, so I looked up the transistor density of tsmc 16nm vs 7nm. 16nm: 28.8 MTr/mm^2 7nm: 96.5 MTr/mm^2 So I think that sifive core with "half the area" is actually not quite as good as a die shrink of the A72.
  - m0zg 7y ago
    >> A72 is a mobile chip So is Apple A13. And yet it's been reported to outperform all Intel desktop CPUs in single core performance (I find the benchmark dubious, but I do believe it's close, and faster than it has any right to be given the super low power consumption). The only reason it doesn't do so in multicore perf is the limited TDP - a concern which does not exist in high end chips. https://news.ycombinator.com/item?id=21033371 https://news.ycombinator.com/item?id=21033371
    - still_grokking 7y ago
      Sure. Even all of Apple's macOS-Server machines running the Apple Cloud are powered by A13 chips these days. /s
      - m0zg 7y ago
        Non sequitur.
  - russler23 7y ago
    Necro-reply here, but yes you got me. 2.63mm2 on 7nm is about 8mm2 on 16nm, which is same as the A72. And it was the A72, the A73's predecessor. I think the point stands that RISC-V is suited for high-performance designs, which was the original contention. If a startup can do 3-way OoO, an org with more resources can do 7-way OoO along with more sophisticated branch prediction and stronger cache coherency to catch up to state-of-the-art cores. There isn't anything in the RISC-V ISA preventing that.
tyingq 7y ago
Interesting view. The SIMD, Vector, and Hypervisor RISCV extensions, as well as things like OoOE seem to contradict your claim. Are you saying they intended to target the high end, and failed? Or that they never intended to target the high end?
- Symmetry 7y ago
  There are a lot of things about the RISCV design that come from a very ideological place and hurt in a high end design. Yes, there are extensions and designs with high end features, that's certainly true, and I'm sure people someone will be making a high end version at some point. But the ISA isn't very well suited to it compared to Power or ARM. By default, code density on RISC-V is pretty bad. You can try to solve that by using variable length instructions which many high end RISC-V projects intend to do but having variable length instructions means your front end is going to have to be more complicated to reach the same level of performance that a fixed width instruction machine can achieve. More instructions for a task means your back end also has to execute more instructions to reach the same level of performance. One way to do better is to fuse together ISA-level instructions into a smaller number of more complex instructions that get executed in your core. This is something that basically every high end design does but RISC-V would have to do it far more extensively than other architectures to achieve a similar level of density on the back end which makes designing a high end core more complex and possibly uses extra pipeline stages making mispredicts more costly. And more more criticisms here: https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d9982f7618ef68 https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d99... EDIT: But in fairness it looks like conditional move might be getting added to the bit manipulation RISC-V extension which would fix one big pain point. This isn't to say that RISC-V is bad. It's simplicity makes it wonderful for low end designs. It's extensibility makes it great for higher level embedded uses where you might want to add some instruction that makes your life easier for your hard driver controller or whatever in a way that would require a very expensive architecture license if you were using ARM. It's open, which would be great if you were making a high end open-source core for other people to use except the Power ISA just opened up so if I were to start a project like that I'd use that instead.
  - 7y ago
mr_toad 7y ago
> No competitive servers can be built with it. Not all servers need to be high end. There’s a big market for small websites.

zozbot234 7y ago

> The RISC-V ISA is pretty awful for high-end designs. No competitive servers can be built with it. I have to dispute this. RISC-V was specifically intended to make high-end designs (i.e. out-of-order architectures, multicore, SMT etc.) not just feasible but relatively easy. It's also designed for extensibility from the ground up, which few others architectures are.

pjc50 7y ago

This argument would benefit from specific examples.

tempguy9999 7y ago

You've not justified this. I'd be very interested in understanding why you make this claim.

russler23 7y ago

That’s funny, SiFive just announced a 3-way OoO RISC-V core. A73 performance, but half the die area. Pretty awful, I guess. https://www.sifive.com/blog/incredibly-scalable-high-performance-risc-v-core-ip https://www.sifive.com/blog/incredibly-scalable-high-perform...

rrss 7y ago
FYI the comparison is to the A72, not A73. A72 is a mobile chip, so still not particularly relevant to tuna-fish's claim about high end servers. The raspberry pi 4 is not a high end server. > half the die area Much of this is free when comparing a 16nm design to a 7nm design. See footnote 1 in your link. EDIT: I was curious, so I looked up the transistor density of tsmc 16nm vs 7nm. 16nm: 28.8 MTr/mm^2 7nm: 96.5 MTr/mm^2 So I think that sifive core with "half the area" is actually not quite as good as a die shrink of the A72.
- m0zg 7y ago
  >> A72 is a mobile chip So is Apple A13. And yet it's been reported to outperform all Intel desktop CPUs in single core performance (I find the benchmark dubious, but I do believe it's close, and faster than it has any right to be given the super low power consumption). The only reason it doesn't do so in multicore perf is the limited TDP - a concern which does not exist in high end chips. https://news.ycombinator.com/item?id=21033371 https://news.ycombinator.com/item?id=21033371
  - still_grokking 7y ago
    Sure. Even all of Apple's macOS-Server machines running the Apple Cloud are powered by A13 chips these days. /s
    - m0zg 7y ago
      Non sequitur.
- russler23 7y ago
  Necro-reply here, but yes you got me. 2.63mm2 on 7nm is about 8mm2 on 16nm, which is same as the A72. And it was the A72, the A73's predecessor. I think the point stands that RISC-V is suited for high-performance designs, which was the original contention. If a startup can do 3-way OoO, an org with more resources can do 7-way OoO along with more sophisticated branch prediction and stronger cache coherency to catch up to state-of-the-art cores. There isn't anything in the RISC-V ISA preventing that.

tyingq 7y ago

Interesting view. The SIMD, Vector, and Hypervisor RISCV extensions, as well as things like OoOE seem to contradict your claim. Are you saying they intended to target the high end, and failed? Or that they never intended to target the high end?

Symmetry 7y ago
There are a lot of things about the RISCV design that come from a very ideological place and hurt in a high end design. Yes, there are extensions and designs with high end features, that's certainly true, and I'm sure people someone will be making a high end version at some point. But the ISA isn't very well suited to it compared to Power or ARM. By default, code density on RISC-V is pretty bad. You can try to solve that by using variable length instructions which many high end RISC-V projects intend to do but having variable length instructions means your front end is going to have to be more complicated to reach the same level of performance that a fixed width instruction machine can achieve. More instructions for a task means your back end also has to execute more instructions to reach the same level of performance. One way to do better is to fuse together ISA-level instructions into a smaller number of more complex instructions that get executed in your core. This is something that basically every high end design does but RISC-V would have to do it far more extensively than other architectures to achieve a similar level of density on the back end which makes designing a high end core more complex and possibly uses extra pipeline stages making mispredicts more costly. And more more criticisms here: https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d9982f7618ef68 https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d99... EDIT: But in fairness it looks like conditional move might be getting added to the bit manipulation RISC-V extension which would fix one big pain point. This isn't to say that RISC-V is bad. It's simplicity makes it wonderful for low end designs. It's extensibility makes it great for higher level embedded uses where you might want to add some instruction that makes your life easier for your hard driver controller or whatever in a way that would require a very expensive architecture license if you were using ARM. It's open, which would be great if you were making a high end open-source core for other people to use except the Power ISA just opened up so if I were to start a project like that I'd use that instead.
- 7y ago

mr_toad 7y ago

> No competitive servers can be built with it. Not all servers need to be high end. There’s a big market for small websites.