5 ms·

Xilinx Vitis and Vitis AI Software Development Platforms

55 points by tfmkevin 7y ago

gsmecher 7y ago
Note that all of this is predicated on High Level Synthesis (HLS) becoming real, after many years of industry over-promises and under-deliveries. A jaded RTL engineer may fairly ask, "what's different this time?" I'm convinced it's two things: 1. These chips have scaled to the point where the toolflow isn't just annoying, it's crippling. (I say that as an RTL designer who likes Vivado, believe it or not.) Making effective use of the largest FPGAs in traditional FPGA applications is difficult enough. Plus, the marginal cost of baking e.g. ARM cores onto an FPGA is now so low that these parts are quickly becoming heterogeneous SoCs and it requires extensive cross-domain knowledge to get a modern design off the ground. More importantly, though, Xilinx is trying to expand FPGAs beyond traditional FPGA markets, and it can't do so without expanding the pool of available talent to program them. Finally, new FPGA applications (e.g. AI) come with their own technical arcana and finding FPGA designers who are proficient in all of these domains is only growing harder. It is necessary for the tools to help, and Xilinx is amply incentivized to pour money into the R&D programs necessary, even if the new tools are simply bundled alongside the old ones. 2. This may be a surprise, but LLVM. Doing HLS correctly is a forced march through every conceivable corner of compiler, language, and RTL design, and to date, that's been much too difficult for EDA companies. I believe that LLVM as an accessible compiler workshop has been instrumental to Xilinx's success to date. I hope Xilinx does genuinely open-source some of the pieces. (Not the synthesis flow, in this case, but all the stuff built on top of it.) The open-source EDA community is small but motivated and talented, but it's crippled by balkanization caused by the commercial EDA market. This might be an interesting shot in the arm.
- spamizbad 7y ago
  I'm curious: why is FPGA tooling so poor? I used a Spartan-3 over a decade ago for a simple project, and as cursory look it doesn't seem like things have changed much despite the devices becoming significantly more diverse and complicated.
  - rowanG077 7y ago
    Mostly because it's (almost) all proprietary. None of the companies are investing in a truly usable solution. It speaks volumes that a handful of developers working for free where able to create a vastly better experience with yosys and friends.
    - 8note 7y ago
      I've always imagined they have a good quality version for military applications, and the bad stuff for everyone else
      - AWildC182 7y ago
        Most of the development is for the military. It gets farmed to contractors who use all the same stuff you have access to, just typically several years out of date. The ability to fully enumerate and simulate every part of the design gives them a huge hardon even though stuff frequently passes simulation and fails on the silicon. It's very common to see FPGAs in nuclear, military RF, and aerospace applications.
      - tfmkevin 7y ago
        There are no separate tools for military use. And, the mil/aero versions of the chips are usually a generation or two behind because of the extra work to make them high-reliability, produce the required documentation, etc.
  - gsmecher 7y ago
    It's not quite fair to say the tooling is flat-out awful. Vivado is much better than ISE. The place/route algorithms matured (analytical placement rather than simulated annealing), and the software it's wrapped in grew up (it's now tcl-driven and much more script- and revision-control-friendly.) Vivado was a heroic effort and Xilinx deserves credit for taking software seriously, and getting so much of it right. If you don't believe me, try hiring an FPGA engineer today to work on an ISE project. You'll get an earful. That said, a solid, open-source, mixed-language simulator with good SystemVerilog and VHDL-2008 support would change my life. Bonus points if I can embed it in C/C++ code a la Verilator. And, while I'm asking, can it simulate encrypted IP too? This is one of the places where HLS may sideswipe the traditional RTL market: if you can effectively develop FPGA designs in C++, the entire approach to development/testing/integration changes completely. It may sound like a detail, but it touches every single pain point associated with a complex FPGA design.
- tfmkevin 7y ago
  HLS is real. I've talked with dozens of teams who have successfully used HLS tools such as Mentor's Catapult, Xilinx's Vivado HLS, and Cadence's Stratus for a wide range of ASIC and FPGA projects. They claim they saw compelling benefits in project schedules, architectural flexibility, and overall performance. However, HLS is still (IMHO) a "power tool" for competent digital designers, not a tool that enables a software designer to create hardware. There is too much hardware-specific expertise required to create good HLS-able code and to do the tradeoffs like pipelining, unrolling, memory architecture, etc etc etc.
kop316 7y ago
"The adoption of FPGA technology in the market has always been limited by the severe learning curve required to take advantage of it." I vehemently disagree with this. FGPAs and their toolchains are notoriously expensive and proprietary. I have no doubt that if tool chains were opened up and an average person could program for it, you would see much more.rapid adoption because then an average person could start the learning curve much easier
- rowanG077 7y ago
  This. It's not so hard, any competent software engineer could learn HDLs in one or two weeks. The fucking toolchain though? Months...
  - enos_feedler 7y ago
    It's a chicken and egg problem too. Toolchain friction and depth of knowledge required is one part. Ubiquity of FPGA silicon lying around in the average programmer's (and end-user's) machine is not there.
    - kbob 7y ago
      Silicon availability has recently been solved. There are FPGA dev boards available for under $50. They're low-powered but great to learn on. One, the FOMU, actually fits inside a USB type-A port.
  - PAGAN_WIZARD 7y ago
    Ive seen plenty of HDL written by people who are software engineers, it's not good. It seems to me most software engineers struggle with visualizing their behavioral code as a schematic and tend to write code that is not very synthesis friendly and overly convoluted. Not to mention most issues with hardware engineering cant be solved by a google search of how to do X in Verilog/VHDL, problems tend to be device specific which means you NEED to understand your tool chain and can't abstract away the code from from the implementation like you can with most high level software to the ASM/binary.

55 points by tfmkevin 7y ago

Note that all of this is predicated on High Level Synthesis (HLS) becoming real, after many years of industry over-promises and under-deliveries. A jaded RTL engineer may fairly ask, "what's different this time?" I'm convinced it's two things: 1. These chips have scaled to the point where the toolflow isn't just annoying, it's crippling. (I say that as an RTL designer who likes Vivado, believe it or not.) Making effective use of the largest FPGAs in traditional FPGA applications is difficult enough. Plus, the marginal cost of baking e.g. ARM cores onto an FPGA is now so low that these parts are quickly becoming heterogeneous SoCs and it requires extensive cross-domain knowledge to get a modern design off the ground. More importantly, though, Xilinx is trying to expand FPGAs beyond traditional FPGA markets, and it can't do so without expanding the pool of available talent to program them. Finally, new FPGA applications (e.g. AI) come with their own technical arcana and finding FPGA designers who are proficient in all of these domains is only growing harder. It is necessary for the tools to help, and Xilinx is amply incentivized to pour money into the R&D programs necessary, even if the new tools are simply bundled alongside the old ones. 2. This may be a surprise, but LLVM. Doing HLS correctly is a forced march through every conceivable corner of compiler, language, and RTL design, and to date, that's been much too difficult for EDA companies. I believe that LLVM as an accessible compiler workshop has been instrumental to Xilinx's success to date. I hope Xilinx does genuinely open-source some of the pieces. (Not the synthesis flow, in this case, but all the stuff built on top of it.) The open-source EDA community is small but motivated and talented, but it's crippled by balkanization caused by the commercial EDA market. This might be an interesting shot in the arm.

spamizbad 7y ago
I'm curious: why is FPGA tooling so poor? I used a Spartan-3 over a decade ago for a simple project, and as cursory look it doesn't seem like things have changed much despite the devices becoming significantly more diverse and complicated.
- rowanG077 7y ago
  Mostly because it's (almost) all proprietary. None of the companies are investing in a truly usable solution. It speaks volumes that a handful of developers working for free where able to create a vastly better experience with yosys and friends.
  - 8note 7y ago
    I've always imagined they have a good quality version for military applications, and the bad stuff for everyone else
    - AWildC182 7y ago
      Most of the development is for the military. It gets farmed to contractors who use all the same stuff you have access to, just typically several years out of date. The ability to fully enumerate and simulate every part of the design gives them a huge hardon even though stuff frequently passes simulation and fails on the silicon. It's very common to see FPGAs in nuclear, military RF, and aerospace applications.
    - tfmkevin 7y ago
      There are no separate tools for military use. And, the mil/aero versions of the chips are usually a generation or two behind because of the extra work to make them high-reliability, produce the required documentation, etc.
- gsmecher 7y ago
  It's not quite fair to say the tooling is flat-out awful. Vivado is much better than ISE. The place/route algorithms matured (analytical placement rather than simulated annealing), and the software it's wrapped in grew up (it's now tcl-driven and much more script- and revision-control-friendly.) Vivado was a heroic effort and Xilinx deserves credit for taking software seriously, and getting so much of it right. If you don't believe me, try hiring an FPGA engineer today to work on an ISE project. You'll get an earful. That said, a solid, open-source, mixed-language simulator with good SystemVerilog and VHDL-2008 support would change my life. Bonus points if I can embed it in C/C++ code a la Verilator. And, while I'm asking, can it simulate encrypted IP too? This is one of the places where HLS may sideswipe the traditional RTL market: if you can effectively develop FPGA designs in C++, the entire approach to development/testing/integration changes completely. It may sound like a detail, but it touches every single pain point associated with a complex FPGA design.
tfmkevin 7y ago
HLS is real. I've talked with dozens of teams who have successfully used HLS tools such as Mentor's Catapult, Xilinx's Vivado HLS, and Cadence's Stratus for a wide range of ASIC and FPGA projects. They claim they saw compelling benefits in project schedules, architectural flexibility, and overall performance. However, HLS is still (IMHO) a "power tool" for competent digital designers, not a tool that enables a software designer to create hardware. There is too much hardware-specific expertise required to create good HLS-able code and to do the tradeoffs like pipelining, unrolling, memory architecture, etc etc etc.

kop316 7y ago

"The adoption of FPGA technology in the market has always been limited by the severe learning curve required to take advantage of it." I vehemently disagree with this. FGPAs and their toolchains are notoriously expensive and proprietary. I have no doubt that if tool chains were opened up and an average person could program for it, you would see much more.rapid adoption because then an average person could start the learning curve much easier

rowanG077 7y ago
This. It's not so hard, any competent software engineer could learn HDLs in one or two weeks. The fucking toolchain though? Months...
- enos_feedler 7y ago
  It's a chicken and egg problem too. Toolchain friction and depth of knowledge required is one part. Ubiquity of FPGA silicon lying around in the average programmer's (and end-user's) machine is not there.
  - kbob 7y ago
    Silicon availability has recently been solved. There are FPGA dev boards available for under $50. They're low-powered but great to learn on. One, the FOMU, actually fits inside a USB type-A port.
- PAGAN_WIZARD 7y ago
  Ive seen plenty of HDL written by people who are software engineers, it's not good. It seems to me most software engineers struggle with visualizing their behavioral code as a schematic and tend to write code that is not very synthesis friendly and overly convoluted. Not to mention most issues with hardware engineering cant be solved by a google search of how to do X in Verilog/VHDL, problems tend to be device specific which means you NEED to understand your tool chain and can't abstract away the code from from the implementation like you can with most high level software to the ASM/binary.