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I was at Semicon Japan last year in December and I learn about the coolest semiconductor company (non profit research organization) ever - MinimalFab [1]. There

I was at Semicon Japan last year in December and I learn about the coolest semiconductor company (non profit research organization) ever - MinimalFab [1]. There isn't much information their website but this [2] video explains what MinimalFab is about. Essentially, it is a cleanroom-free, modularized fab where each process step in a fab is like a little ATM machine. Miniaturization of complex fab processes is mind blowing and everything is contained inside the machine including a Class 100 environment. Load a tiny quarter sized wafer in a cassette to process and move material from one machine to another. This kind of a fab setup would be incredibly useful to R&D fabs in universities and small scale fabrication for military, space, defense and perhaps even hobby use. [1] https://www.minimalfab.com/en/ https://www.minimalfab.com/en/ [2] https://www.youtube.com/watch?v=WsOVbmfYxoM https://www.youtube.com/watch?v=WsOVbmfYxoM

dbcurtis 7y ago
That looks very exciting for some research environments, and for some prototyping. But a 12mm wafer is certainly going to limit what you can do, and they make no mention of feature size. In the end, what you can accomplish is determined by the process and how easily your design tools let you target the process. I am sure there is a lot of academic research that could benefit greatly. As to prototyping, I have concerns that it would be difficult to do a part on this process and transfer it to a different process for scale.
LargoLasskhyfv 7y ago
That is very interesting! I watched that and found some more information after searching a little: [1] https://www.yokogawa.com/yjp/solutions/solutions/minimal-fab/ https://www.yokogawa.com/yjp/solutions/solutions/minimal-fab... It seems like this fab is a demonstrator, and is planned for sale. This makes me wonder if/when this will be available for maker style setups, at which process nodes & price per piece. Would be nice to be able to design some fully custom ip, have it tested, bonded and packaged, and optionally soldered, like you can have it with pcb services today. One can dream, yes?
- LargoLasskhyfv 7y ago
  Found another, more technical video, but couldn't recognize anything about process node/feature size. Anyways, here it is: [1] https://www.youtube.com/watch?v=hViCDab0E2A https://www.youtube.com/watch?v=hViCDab0E2A
  - LargoLasskhyfv 7y ago
    Nikkei Article from December 2016 mentioning 0.8 micron, while aiming for 0.35 micron in 2018. So that's it, i guess? [1] https://asia.nikkei.com/Business/Biotechnology/Minimal-fab-tech-promises-faster-cheaper-chip-production https://asia.nikkei.com/Business/Biotechnology/Minimal-fab-t... According to wikipedia the following CPUs were built with that: [2] https://en.wikipedia.org/wiki/350_nanometer https://en.wikipedia.org/wiki/350_nanometer Which i think of as more than sufficient to finally being able to implement something like SCED, WAM, CHERI, Applecore, whatever in whichever way one is able to wrap his brains around it. Asynchronous, fully static? https://en.wikipedia.org/wiki/Mead_%26_Conway_revolution https://en.wikipedia.org/wiki/Mead_%26_Conway_revolution (with MEMS(for sensing)) from scratch? I want it all! I want it NOW!
    - hollerith 7y ago
      That's cool, but your [1] seems to say that the machine uses a wafer 12.5 mm in diameter, which is is probably less area than any of the CPUs in your [2].
      - LargoLasskhyfv 7y ago
        Should suffice for my needs, see for example here [1] https://en.wikipedia.org/wiki/R4200 https://en.wikipedia.org/wiki/R4200 under R4300i which mentions 45mm² for the die. Also mentioned here [2] https://bits-chips.nl/artikel/small-series-of-chips-profitable-by-flexible-concept-minimal-fab/ https://bits-chips.nl/artikel/small-series-of-chips-profitab... are 0.25-micron to be released this year, with 190nm and smaller on the roadmap. Which leads us to [3] https://en.wikipedia.org/wiki/250_nanometer https://en.wikipedia.org/wiki/250_nanometer at least. Maybe not comparable in die size for all the chips mentioned there, i don't care so much, because i don't want to clone or emulate them. I want to go simpler. Rebranch from the 70ies so to speak, to take all the roads not taken since then. Just to see what's there :-)
ChuckMcM 7y ago
That is exceptionally cool. They have taken existing best practices in semiconductor fabs and migrated them to an interesting place. What is missing of course is what their feature sizes are and the part at the end where you cut the die and package it. It is those things that would define the set of things you could put on a single chip.
- LargoLasskhyfv 7y ago
  Have a look at [1] https://bits-chips.nl/artikel/small-series-of-chips-profitable-by-flexible-concept-minimal-fab/ https://bits-chips.nl/artikel/small-series-of-chips-profitab... under "E-Beam" for 0.25-micron node and roadmap.
  - ChuckMcM 7y ago
    Ok thanks for that. So 500 nm today, moving to 250 nm by the end of the year or early next year. So your 12.5mm wafer can have a 8.8 x 8.8 mm square inside of it, or 78.125 mm^2. If I did the math right that is on the order of 156M transistors given a 4t ram cell that is about 39 million bits of RAM. So basically a pretty useful amount of space for "jelly bean" type applications. A synchronized fab line with a median processing time of 1 minute can produce 60 dice per hour. Assuming a physical plant cost of $8M US (that is "several million Euros + the office space to hold it) and a depreciation cycle of 12 years that is about $500 / day for the machinery we can add another $500 / day for staff + electricity, figuring 8 hour days, that's $125/hour to operate for 60 chips is a bit more than $2/dice. Well the pencil math works (with all of those assumptions) but even assuming its off by an order of magnitude, $20/dice isn't a deal breaker for your own custom chip that does your special thing. You'll also notice that the 50 weeks a year 40 hours a week assumption. I'm guessing you can get better utilization than that which would offset your depreciation costs.
    - LargoLasskhyfv 7y ago
      Here is a PDF from 2017 from someone involved with a project wich seems to intend to use this in an (large scale?) innovation initiative in Japan. [1] www.lip6.fr/public/2017-03-17_Shimizu.pdf Mentioned are workflows, used tools, intendend audience and goals, estimated prices, nda-freeness of spice models and design rule check, open source, open-cores, github, and so on. If they really make this widely available, then my mind is blown...
rramadass 7y ago
Damn! Thanks for this info.
amelius 7y ago
Small production sizes are cool, but you still have to factor in yield of course.

dbcurtis 7y ago

That looks very exciting for some research environments, and for some prototyping. But a 12mm wafer is certainly going to limit what you can do, and they make no mention of feature size. In the end, what you can accomplish is determined by the process and how easily your design tools let you target the process. I am sure there is a lot of academic research that could benefit greatly. As to prototyping, I have concerns that it would be difficult to do a part on this process and transfer it to a different process for scale.

LargoLasskhyfv 7y ago

That is very interesting! I watched that and found some more information after searching a little: [1] https://www.yokogawa.com/yjp/solutions/solutions/minimal-fab/ https://www.yokogawa.com/yjp/solutions/solutions/minimal-fab... It seems like this fab is a demonstrator, and is planned for sale. This makes me wonder if/when this will be available for maker style setups, at which process nodes & price per piece. Would be nice to be able to design some fully custom ip, have it tested, bonded and packaged, and optionally soldered, like you can have it with pcb services today. One can dream, yes?

LargoLasskhyfv 7y ago
Found another, more technical video, but couldn't recognize anything about process node/feature size. Anyways, here it is: [1] https://www.youtube.com/watch?v=hViCDab0E2A https://www.youtube.com/watch?v=hViCDab0E2A
- LargoLasskhyfv 7y ago
  Nikkei Article from December 2016 mentioning 0.8 micron, while aiming for 0.35 micron in 2018. So that's it, i guess? [1] https://asia.nikkei.com/Business/Biotechnology/Minimal-fab-tech-promises-faster-cheaper-chip-production https://asia.nikkei.com/Business/Biotechnology/Minimal-fab-t... According to wikipedia the following CPUs were built with that: [2] https://en.wikipedia.org/wiki/350_nanometer https://en.wikipedia.org/wiki/350_nanometer Which i think of as more than sufficient to finally being able to implement something like SCED, WAM, CHERI, Applecore, whatever in whichever way one is able to wrap his brains around it. Asynchronous, fully static? https://en.wikipedia.org/wiki/Mead_%26_Conway_revolution https://en.wikipedia.org/wiki/Mead_%26_Conway_revolution (with MEMS(for sensing)) from scratch? I want it all! I want it NOW!
  - hollerith 7y ago
    That's cool, but your [1] seems to say that the machine uses a wafer 12.5 mm in diameter, which is is probably less area than any of the CPUs in your [2].
    - LargoLasskhyfv 7y ago
      Should suffice for my needs, see for example here [1] https://en.wikipedia.org/wiki/R4200 https://en.wikipedia.org/wiki/R4200 under R4300i which mentions 45mm² for the die. Also mentioned here [2] https://bits-chips.nl/artikel/small-series-of-chips-profitable-by-flexible-concept-minimal-fab/ https://bits-chips.nl/artikel/small-series-of-chips-profitab... are 0.25-micron to be released this year, with 190nm and smaller on the roadmap. Which leads us to [3] https://en.wikipedia.org/wiki/250_nanometer https://en.wikipedia.org/wiki/250_nanometer at least. Maybe not comparable in die size for all the chips mentioned there, i don't care so much, because i don't want to clone or emulate them. I want to go simpler. Rebranch from the 70ies so to speak, to take all the roads not taken since then. Just to see what's there :-)

ChuckMcM 7y ago

That is exceptionally cool. They have taken existing best practices in semiconductor fabs and migrated them to an interesting place. What is missing of course is what their feature sizes are and the part at the end where you cut the die and package it. It is those things that would define the set of things you could put on a single chip.

LargoLasskhyfv 7y ago
Have a look at [1] https://bits-chips.nl/artikel/small-series-of-chips-profitable-by-flexible-concept-minimal-fab/ https://bits-chips.nl/artikel/small-series-of-chips-profitab... under "E-Beam" for 0.25-micron node and roadmap.
- ChuckMcM 7y ago
  Ok thanks for that. So 500 nm today, moving to 250 nm by the end of the year or early next year. So your 12.5mm wafer can have a 8.8 x 8.8 mm square inside of it, or 78.125 mm^2. If I did the math right that is on the order of 156M transistors given a 4t ram cell that is about 39 million bits of RAM. So basically a pretty useful amount of space for "jelly bean" type applications. A synchronized fab line with a median processing time of 1 minute can produce 60 dice per hour. Assuming a physical plant cost of $8M US (that is "several million Euros + the office space to hold it) and a depreciation cycle of 12 years that is about $500 / day for the machinery we can add another $500 / day for staff + electricity, figuring 8 hour days, that's $125/hour to operate for 60 chips is a bit more than $2/dice. Well the pencil math works (with all of those assumptions) but even assuming its off by an order of magnitude, $20/dice isn't a deal breaker for your own custom chip that does your special thing. You'll also notice that the 50 weeks a year 40 hours a week assumption. I'm guessing you can get better utilization than that which would offset your depreciation costs.
  - LargoLasskhyfv 7y ago
    Here is a PDF from 2017 from someone involved with a project wich seems to intend to use this in an (large scale?) innovation initiative in Japan. [1] www.lip6.fr/public/2017-03-17_Shimizu.pdf Mentioned are workflows, used tools, intendend audience and goals, estimated prices, nda-freeness of spice models and design rule check, open source, open-cores, github, and so on. If they really make this widely available, then my mind is blown...

rramadass 7y ago

Damn! Thanks for this info.

amelius 7y ago

Small production sizes are cool, but you still have to factor in yield of course.