3 ms·
They may need to access main memory, but the RMW operation don't happen over the memory bus. The processor appropriates the cache line just like any other memor
by bonzini 7y ago
They may need to access main memory, but the RMW operation don't happen over the memory bus. The processor appropriates the cache line just like any other memory access, and then operates atomically on the cache line.
- amelius 7y agoAnd what if the cache line is full/dirty?
- bonzini 7y agoThe cache coherency protocol takes care of that. In other words the first part is just a memory load and can vary from 0 to a few hundred clock cycles, the second is local to the processor and has a more or less fixed cost. The worst-case execution time is completely dominated by the first part, the best case instead is dominated by the second.
- jasonwatkinspdx 7y agoI'd suggest reading the wiki articles about it for an introduction, and Ch 5 of https://www.amazon.com/Computer-Architecture-Quantitative-John-Hennessy/dp/012383872X https://www.amazon.com/Computer-Architecture-Quantitative-Jo... for a detailed understanding. Right now you're asserting things about all this, while not being familiar with relatively basic aspects of how it works.