4 ms·

• Research chip • IA-32 • 48 cores, 24 tiles of 2 cores each • ☞ Caches are not coherent ☜ • On chip message passing system between tiles • Application lev

• merijnv 16y ago
  The chip is (in theory) very interesting to work with, but in practice it suffers a lot due to lack of cache control. Since the L2 cache is writeback (instead of write-through) and because there is no cache flush instruction you are forced to manually flush your cache by reading from memory...
  • jws 16y ago
    I think that is the point. If people are willing to program in this paradigm (message passing), then 1000+ core chips are possible. I think the question becomes: For problems decomposed into a message passing solution, is a 15x speedup for on die message passing a win at the 1000 core scale? Or another way around, for the scale problems that work at 1000 cores, is the message passing overhead is negligible and you can just as well stick them on separate dies/modules/blades/racks.
    • merijnv 16y ago
      I agree that no cache coherency is the entire point of the chip, but the lack of manual control over things like flushing the cache is entirely unrelated to cache coherency and a significant issue in some of the things we've been trying to do on the chip.
• skorgu 16y ago
  Seems very similar to Larrabee.
  • corysama 16y ago
    "48 Pentium-class IA-32 cores". It is Larrabee (or some branch of it). The most interesting feature of Larrabee that is not mentioned in the article was the 16-way scatter-gather memory operations. That feature made the 16x32bit SIMD operations much more practical to use. If you could manage to set up large blocks of mostly branchless work, you could get an effective 48*16=768 way parallelism. Not good for running interpreters, but very good for math and data crunching.
    • wmf 16y ago
      No, SCC is quite different from Larrabee; it uses a mesh instead of a ring, lacks the vector unit, lacks cache coherence, etc.