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Intel Lifts the Hood on its "Single-Chip Cloud Computer"
- jws 16y ago• Research chip • IA-32 • 48 cores, 24 tiles of 2 cores each • ☞ Caches are not coherent ☜ • On chip message passing system between tiles • Application level voltage/frequency control to manage power • 25 to 125 watts, 1.3B transistors • Has booted Linux
- merijnv 16y agoThe chip is (in theory) very interesting to work with, but in practice it suffers a lot due to lack of cache control. Since the L2 cache is writeback (instead of write-through) and because there is no cache flush instruction you are forced to manually flush your cache by reading from memory...
- jws 16y agoI think that is the point. If people are willing to program in this paradigm (message passing), then 1000+ core chips are possible. I think the question becomes: For problems decomposed into a message passing solution, is a 15x speedup for on die message passing a win at the 1000 core scale? Or another way around, for the scale problems that work at 1000 cores, is the message passing overhead is negligible and you can just as well stick them on separate dies/modules/blades/racks.
- merijnv 16y agoI agree that no cache coherency is the entire point of the chip, but the lack of manual control over things like flushing the cache is entirely unrelated to cache coherency and a significant issue in some of the things we've been trying to do on the chip.
- skorgu 16y agoSeems very similar to Larrabee.
- corysama 16y ago"48 Pentium-class IA-32 cores". It is Larrabee (or some branch of it). The most interesting feature of Larrabee that is not mentioned in the article was the 16-way scatter-gather memory operations. That feature made the 16x32bit SIMD operations much more practical to use. If you could manage to set up large blocks of mostly branchless work, you could get an effective 48*16=768 way parallelism. Not good for running interpreters, but very good for math and data crunching.
- wmf 16y agoNo, SCC is quite different from Larrabee; it uses a mesh instead of a ring, lacks the vector unit, lacks cache coherence, etc.
- patrickgzill 16y agoThis doesn't seem so exciting once you realize that AMD and Intel are already shipping 12-core CPUs.
- InclinedPlane 16y agoAre they? I believe they are shipping 6-core CPUs with hyper-threading (which present to the OS as 12-cores), but I'm not aware of them shipping chips with 12 physical cores. Care to cite an example?
- wmf 16y agoIntel is shipping 8-core (Xeon 7500) and AMD has a 12-core MCM (two 6-cores) (Opteron 6100).
- zmanian 16y agoBeyond approx 32 cores, cache coherent architectures don't scale. Intel faces enormous pressure to find consumer applications for message passing chip architectures otherwise the post 32 cores chips will be low volume products. Intel has been working very hard to find collaborators with application concepts for this era. Having this product permitts Intel to give them hardware rather that just FPGA simulators
- wmf 16y agoBeyond approx 32 cores, cache coherent architectures don't scale. It's not clear that this is true. Tilera is shipping 64 cores and working on 100.
- ajays 16y agoDated: 9 February 2010