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Do these techniques make it easier or harder to implement hardware floating point units? Storage and transmission speed have progressed exponentially while exe

by yholio 7y ago

Do these techniques make it easier or harder to implement hardware floating point units? Storage and transmission speed have progressed exponentially while execution units have become the bottleneck. A floating point format that is 20% denser or more accurate but that requires a 2x number of gate delays to implement is major step backwards, except maybe in highly specialized applications.

yaantc 7y ago
From [1]: " The standard 32 bits posit adder is found to be twice as large as the corresponding floating-point adder. Posit multiplication requires about 7 times more LUTs and a few more DSPs for a latency which is 2x worst than the IEEE-754 32 bit multiplier." It's for an FPGA implementation. This being said, I object to your premise: transmission and memory storage are getting comparatively more costly vs computation. From "Computer Architecture, A Quantitative Approach", 6th edition in figure 1.13 there are some values for the TSMC 45nm process, so hardly the leading edge and it only gets worse with finer nodes: - 32 bits integer multiplication: 3.2 pJ - 32 bits float multiplication: 3.7 pJ - 32 bits read in a small 8 kB SRAM: 5 pJ - external DRAM 32 bits read: 640 pJ We have a lot of transistor nowadays, and as long as the computation can be pipelined halving the memory accesses could be a win (TBC). Also on from the same Inria team as [1], and also covering hardware cost but more than this: "Posits: the good, the bad and the ugly": https://hal.inria.fr/hal-01959581v3/document https://hal.inria.fr/hal-01959581v3/document [1] "Hardware cost evaluation of the posit number system", https://hal.inria.fr/hal-02131982/document https://hal.inria.fr/hal-02131982/document
- dnautics 7y ago
  I'm not sure the inria team used the correct optimization for posit addition. You do yourself a disservice by treating a posit like a float and bifurcate the cross (negative/positive) from the negative/negative and positive/positive branches; since posits are twos complements the posit adder should be smaller, not bigger.
sitkack 7y ago
> transmission speed Memory bandwidth relative to instruction to instruction latency has gone way down. Memory is slower now relative to the amount of math one can do. We are also swimming in extra silicon, so even if what you are saying is true (2x the number of gates, all adding to the delay), posits would still be a win. You are arguing from an arbitrary what-if position, it doesn't look good.

by yholio 7y ago

yaantc 7y ago

From [1]: " The standard 32 bits posit adder is found to be twice as large as the corresponding floating-point adder. Posit multiplication requires about 7 times more LUTs and a few more DSPs for a latency which is 2x worst than the IEEE-754 32 bit multiplier." It's for an FPGA implementation. This being said, I object to your premise: transmission and memory storage are getting comparatively more costly vs computation. From "Computer Architecture, A Quantitative Approach", 6th edition in figure 1.13 there are some values for the TSMC 45nm process, so hardly the leading edge and it only gets worse with finer nodes: - 32 bits integer multiplication: 3.2 pJ - 32 bits float multiplication: 3.7 pJ - 32 bits read in a small 8 kB SRAM: 5 pJ - external DRAM 32 bits read: 640 pJ We have a lot of transistor nowadays, and as long as the computation can be pipelined halving the memory accesses could be a win (TBC). Also on from the same Inria team as [1], and also covering hardware cost but more than this: "Posits: the good, the bad and the ugly": https://hal.inria.fr/hal-01959581v3/document https://hal.inria.fr/hal-01959581v3/document [1] "Hardware cost evaluation of the posit number system", https://hal.inria.fr/hal-02131982/document https://hal.inria.fr/hal-02131982/document

dnautics 7y ago
I'm not sure the inria team used the correct optimization for posit addition. You do yourself a disservice by treating a posit like a float and bifurcate the cross (negative/positive) from the negative/negative and positive/positive branches; since posits are twos complements the posit adder should be smaller, not bigger.

sitkack 7y ago

> transmission speed Memory bandwidth relative to instruction to instruction latency has gone way down. Memory is slower now relative to the amount of math one can do. We are also swimming in extra silicon, so even if what you are saying is true (2x the number of gates, all adding to the delay), posits would still be a win. You are arguing from an arbitrary what-if position, it doesn't look good.