3 ms·
Sidestepping Moore’s Law
- kurthr 7y agoI'm surprised there's no discussion of wafer level stacking and interconnect. I suppose that's mostly done at the foundry, but stacking digital with memory and/or flash could have real bandwidth and performance effects.
- sanxiyn 7y agoIsn't that what "2.5D" in the article refers to?
- AChamarthy 7y ago2.5D is connecting chips laterally on an interposer. Full 3D IC wafer level Packaging would be stacking wafers on top of each other a in dense, heterogenous, 3D configuration - i.e. "memory near compute" Ex: https://www.kurzweilai.net/radical-new-vertically-integrated-3d-chip-design-combines-computing-and-data-storage https://www.kurzweilai.net/radical-new-vertically-integrated...