3 ms·
The part you quoted is a part of a thought experiment. The author is explicitly saying that Verilog is _not_ an ISA: > By way of contradiction, let’s imagine w
by rachitnigam 7y ago
The part you quoted is a part of a thought experiment. The author is explicitly saying that Verilog is _not_ an ISA:
> By way of contradiction, let’s imagine what it would look like if RTL were playing each of these roles well.
The point of this section was to point out that the set of people who use FPGAs as accelerators (a la MSFT catapult) use it with the ISA abstraction: they don’t want to care about he timing, they just want to get the dataflow graph to accelerate the computation.
Disclaimer: I work with the author of the article on acceleration architectures and languages.
- Traster 7y agoRight but people who use FPGAs as accelerators a la MSFT catapult went to Altera and asked them specifically to write and ship RTL to enable them to do so. They use it with an ISA abstraction because they bought so many chips that Altera did a big chunk of the design work for them. That's a valid approach but I wouldn't say that's really doing FPGA design.
- lvoudour 7y agoRegarding the end of the article: A new category of hardware that beats FPGAs at their own game could bring with it a fresh abstraction hierarchy. The new software stack should dispense with FPGAs’ circuit emulation legacy and, with it, their RTL abstraction Are you or the author working on something along these lines and if so can you give an example? I'll tell you the truth I was expecting a proposition and I felt kind of "robbed" when I reached the end and no alternative was given