5 ms·

Researchers break “memory wall” conundrum, create fastest optical RAM cell

53 points by conse_lad 7y ago

p1esk 7y ago
How dense is it?
- dvh 7y ago
  5x10x1cm
  - p1esk 7y ago
    :) ok, how dense can it be?
    - Etheryte 7y ago
      As covered in the article [1, paywalled], the binary cell itself consists of two flipflops, each at 6x2 mm², and an optical xor (no dimensions given). So for the time being, most of the space is in the control logic, as would be expected for a first proof of concept. Currently, the answer to your question seems "not very", but if the tech proves to be viable it will certainly attract a lot of further research & funding to minimize it. Compare first proof of concept memory cells vs what followed in the years to come. [1] https://www.osapublishing.org/ol/abstract.cfm?uri=ol-44-7-1821 https://www.osapublishing.org/ol/abstract.cfm?uri=ol-44-7-18...
      - p1esk 7y ago
        Haven’t read the article yet, but I wonder if this technology can ever compete with SRAM on any of speed/density/power? Or is it intended strictly for an “all optical” processor?
Dylan16807 7y ago
So what is this memory wall? > this concept revolves around the idea that computer processing units (CPUs) are advancing at a fast enough pace that will leave memory (RAM) stagnant > According to Moore’s Law, which states that the number of transistors in a circuit doubles every two years, CPUs will eventually become too fast to yield any noticeable difference in computing speed. Once we reach this so-called memory wall, program/app execution time will depend almost entirely on the speed at which RAM can send data to the CPU. So even if you have an incredibly fast processor in your computer, it’s function may be limited to the speed of your RAM. Oh, it's utter nonsense. For one, it's ignoring that the cache speeds scale right along with the CPU. You could get rid of DRAM entirely to prove there is no 'wall'. But what really kills the argument is a proper analysis of how memory is set up. Internal to the RAM chip, there's a ridiculous amount of bandwidth. The bottleneck is using a 64-bit-wide bus to communicate with the CPU. But that bottleneck is only a cost saving measure on top of Moore's Law. If we back off to pure Moore's Law, we can quite easily add more and more memory width/channels and not hit any limits.
- deleted 7y ago
  [deleted]
- dokem 7y ago
  It's not just about bandwidth but latency. Sure I can double the bandwidth by widening the bus but that won't get me any closer to servicing a r/w request within a clock cycle and remove the need for memory stalling.
  - Dylan16807 7y ago
    Latency exists. But they're talking about it being literally impossible to feed the cores. Nonsense. One memory channel per (modern-ish) core is always going to be able to feed it.
- p1esk 7y ago
  cache speeds scale right along with the CPU This is true only for L1 cache. If you’re ok with having 64KB total memory in your computer then sure. Re memory bus width: you’re forgetting about latency. Also, a wider bus is usually a slower (in terms of frequency) bus, for multiple reasons.
peter_d_sherman 7y ago
This article is why I read Hacker News! To surpass limitations; and see limitations surpassed, in all areas of technology. This article exemplifies that ethos. This is the future, or rather a glimpse of it, today. Well done!

53 points by conse_lad 7y ago

p1esk 7y ago

How dense is it?

dvh 7y ago
5x10x1cm
- p1esk 7y ago
  :) ok, how dense can it be?
  - Etheryte 7y ago
    As covered in the article [1, paywalled], the binary cell itself consists of two flipflops, each at 6x2 mm², and an optical xor (no dimensions given). So for the time being, most of the space is in the control logic, as would be expected for a first proof of concept. Currently, the answer to your question seems "not very", but if the tech proves to be viable it will certainly attract a lot of further research & funding to minimize it. Compare first proof of concept memory cells vs what followed in the years to come. [1] https://www.osapublishing.org/ol/abstract.cfm?uri=ol-44-7-1821 https://www.osapublishing.org/ol/abstract.cfm?uri=ol-44-7-18...
    - p1esk 7y ago
      Haven’t read the article yet, but I wonder if this technology can ever compete with SRAM on any of speed/density/power? Or is it intended strictly for an “all optical” processor?

Dylan16807 7y ago

So what is this memory wall? > this concept revolves around the idea that computer processing units (CPUs) are advancing at a fast enough pace that will leave memory (RAM) stagnant > According to Moore’s Law, which states that the number of transistors in a circuit doubles every two years, CPUs will eventually become too fast to yield any noticeable difference in computing speed. Once we reach this so-called memory wall, program/app execution time will depend almost entirely on the speed at which RAM can send data to the CPU. So even if you have an incredibly fast processor in your computer, it’s function may be limited to the speed of your RAM. Oh, it's utter nonsense. For one, it's ignoring that the cache speeds scale right along with the CPU. You could get rid of DRAM entirely to prove there is no 'wall'. But what really kills the argument is a proper analysis of how memory is set up. Internal to the RAM chip, there's a ridiculous amount of bandwidth. The bottleneck is using a 64-bit-wide bus to communicate with the CPU. But that bottleneck is only a cost saving measure on top of Moore's Law. If we back off to pure Moore's Law, we can quite easily add more and more memory width/channels and not hit any limits.

deleted 7y ago
[deleted]
dokem 7y ago
It's not just about bandwidth but latency. Sure I can double the bandwidth by widening the bus but that won't get me any closer to servicing a r/w request within a clock cycle and remove the need for memory stalling.
- Dylan16807 7y ago
  Latency exists. But they're talking about it being literally impossible to feed the cores. Nonsense. One memory channel per (modern-ish) core is always going to be able to feed it.
p1esk 7y ago
cache speeds scale right along with the CPU This is true only for L1 cache. If you’re ok with having 64KB total memory in your computer then sure. Re memory bus width: you’re forgetting about latency. Also, a wider bus is usually a slower (in terms of frequency) bus, for multiple reasons.

peter_d_sherman 7y ago

This article is why I read Hacker News! To surpass limitations; and see limitations surpassed, in all areas of technology. This article exemplifies that ethos. This is the future, or rather a glimpse of it, today. Well done!