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Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor
- phkahler 7y agoHas the vector spec been finalized yet? I think it will be critical to bring graphics to RISCV.
- orbifold 7y agoGraphics is much more subtle than just vector instructions as can be seen from the failures of Larrabee.
- tjoff 7y agoI'd imagine Larrabees failures primarily has been being competitive with AMD and nVidia?
- erik 7y agoLarrabee had dedicated texturing hardware, but management decided to not expose it or try shipping it as a GPU.
- phkahler 7y ago>> Graphics is much more subtle than just vector instructions as can be seen from the failures of Larrabee. It is. But given there are zero other open source solutions, I think LLVM Pipe running on the vector extension would be a decent option. It's not going to compete with the big guys, but it will make SoCs possible without licensing grahpics IP.
- nickik 7y agoYes. But the RISC-V Vector instruction will serve as the baseline. And further extensions will add register types, Esperanto is already extending them with graphic types.
- fluffything 7y agoNote that RISCV vector extension also supports matrices, tensors, etc. So at least for GPGPU compute applications, it feels quite modern (e.g. Volta has tensor cores). Also, Larrabee had fixed-width 512-bit wide vectors (it did not support SSE 128-bit wide or AVX 256-bit wide vectors). RISC-V has Cray vectors of dynamic length (e.g. need a 128-bit vector, no problem, need a 4096 bit one? no problem either). I think the main issue for programming CPUs to solve GPU problems is that our programming models for CPUs don't expose the memory hierarchy, while the ones for GPUs do that in a much more finer grained way.
- nullwasamistake 7y agoMemory bandwidth is another issue holding CPUs back
- _chris_ 7y agoIt's still a work-in-progress, but there should be some interesting news at the RISC-V Zurich conference next week [1]. For example, Imperas has announced an ISA simulator for the current 0.71 version of the specification [2]. [1] (https://tmt.knect365.com/risc-v-workshop-zurich/agenda/1 https://tmt.knect365.com/risc-v-workshop-zurich/agenda/1) [2] (http://imperas.com/articles/imperas-delivers-first-risc-v-simulator-for-new-vector-and-bit-manipulation-specifications http://imperas.com/articles/imperas-delivers-first-risc-v-si...)
- childintime 7y ago> at the RISC-V Zurich conference next week Curiously this session is only 15 minutes long. June 11, 17:45 - 18:00, by Krste Asanovic. Nevertheless it is quite promising: "Vector Extension 0.7. The vector extensions have reached a major milestone with the release of version 0.7, which is intended for widespread implementation and comment". Excellent news.
- _chris_ 7y agoThere were a ton of talk submissions, and the schedule is incredibly tight because of it. =(
- dmos62 7y agoCommentary? What's the difference between a GPU and a vector processor? Is vector processors being open-source a desirable quality (compared to general attractiveness of open-source)?
- wolf550e 7y agoI think they mean something like SSE/AVX, but with something like ARM Scalable Vector Extension (code that works on registers with 128 to 2048 bit size, unknown at compile time).
- theonlyklas 7y agoFrom: https://theincredibleholk.wordpress.com/2012/10/26/are-gpus-just-vector-processors/ https://theincredibleholk.wordpress.com/2012/10/26/are-gpus-... > Under this model, each SM on an NIVIDA GPU corresponds to a more traditional CPU core. These SMs would contain some number of 32-wide vector registers. It seems that CUDA exposes operations on vector registers as a warp. They appear to be 32 threads because each instruction on 32 lanes at once, while the threads must proceed in lock step because they are actually a single stream of instructions. >Is vector processors being open-source a desirable quality (compared to general attractiveness of open-source)? Absolutely. Imagine an initiative to create a standardized open-source GPU for Linux? This vector processor could provide open source silicon IP to help build it. This chip is just another step towards fully open-source systems.
- rbanffy 7y ago> Imagine an initiative to create a standardized open-source GPU for Linux? A CPU that can do number crunching like a GPU as well as general purpose computing would be amazing.
- nickpsecurity 7y agoThe Web really needs a good resource on answering this question. I didn't see one in quick search. These links each have pieces of the answer: https://www.inf.ed.ac.uk/teaching/courses/pa/Notes/lecture11-vector.pdf https://www.inf.ed.ac.uk/teaching/courses/pa/Notes/lecture11... https://stackoverflow.com/questions/49098533/vpu-vs-fpu-vs-gpu-vs-alu https://stackoverflow.com/questions/49098533/vpu-vs-fpu-vs-g... https://www.quora.com/What-is-the-main-difference-between-SIMD-and-GPU https://www.quora.com/What-is-the-main-difference-between-SI...
- amelius 7y agoDoes it have speculative execution vulnerabilities?
- DSingularity 7y agoThere doesn’t look to be any speculation in this architecture.
- scottlamb 7y ago> Ara runs at 1.2 GHz in the typical corner (TT/0.80 V/25 oC), achieving a performance up to 34 DP-GFLOPS. In terms of energy efficiency, Ara achieves up to 67 DP-GFLOPS/W under the same conditions, which is 56% higher than similar vector processors found in literature. I wonder if it supports vectorized 8-bit multiplies and, if so, what its performance and efficiency is on those. I've been looking around at AI accelerators a bit recently. They AFAIK only do 8-bit operations and are rated in TOPS (tera-operations-per-second). Google's Coral USB Accelerator (with an Edge TPU chip) claims 4 TOPS, at 2 TOPS/W. The Gyrfalcon Plai Plug (with a SPR2801S chip) claims 5.6 TOPS, at 9.3 TOPS/W. It'd be really exciting to have an open architecture chip match or exceed that. The Kendryte K210 is a RISC-V AI accelerator chip announced recently, but it only claims 0.25 TOPS, or 0.8 TOPS/W.
- bobajeff 7y agoThanks. A lot of people here seem to focus on Computer Graphics I'm also wondering about potential application Machine Learning and Neural Networks. Like how would it fare against today's FPGAs, DSP, NPU and TPUs?
- ncmncm 7y agoBefore I can be bullish on RISC-V, I really need to see a set of basic bitwise instructions -- minimally, popcount and count-leading-zeros (i.e. integer log-base-2). When I last looked at the (tabled) bitwise extensions, they had been bloated out of all reason with really wild bit-shuffling apparatus. I understand those last are very useful to some people, but if they interfere with getting a fast popcount in the core ISA, we can't afford them.
- zzo38computer 7y agoI would like at least popcount (or, alternatively, the "sideways add" in MMIX, which does popcount(x&~y)) and "multiple or" (another instruction in MMIX).
- smallstepforman 7y agoThe whole point of Risc is to avoid instruction complexity for rarely used instructions. Popcount and family are most likely microcoded to expand to a loop anyway, so why add this complexity to silicon?
- pjscott 7y agoI checked the latency and throughput of the SSE4 POPCNT and LZCNT instructions on a bunch of microarchitectures [1], and can't think of any way to get that kind of performance with a combination of simpler instructions. These are occasionally very useful operations, and I really do want them to be fast. [1] https://www.agner.org/optimize/instruction_tables.pdf https://www.agner.org/optimize/instruction_tables.pdf
- vardump 7y ago> The whole point of Risc is to avoid instruction complexity for rarely used instructions Yeah, that was true 20-30 years ago. > Popcount and family are most likely microcoded to expand to a loop anyway, so why add this complexity to silicon? No, you can just make a network of small adders. You could easily build a CPU that has throughput of 1 popcount per cycle (or even better, if SIMD and/or multiple execution ports supported this ALU operation). Silicon area is not a problem anyways anymore. Power and heat on the other hand...
- alexnewman 7y agoIt's really happening
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- erichocean 7y agoRISC-V sponsors need to spend the money on developers getting ISPC to target whatever the RISC-V Vector spec ends up being. Without that, you'd have to rely on auto-vectorization and that's not great for anything but HPC applications using OpenMP.