4 ms·

Interesting paper. The original concept is at http://people.csail.mit.edu/sanchez/papers/2018.hotpads.micro.pdf http://people.csail.mit.edu/sanchez/papers/2018.

by foota 7y ago

Interesting paper. The original concept is at http://people.csail.mit.edu/sanchez/papers/2018.hotpads.micro.pdf http://people.csail.mit.edu/sanchez/papers/2018.hotpads.micr..., and the follow up paper the article is written about is https://people.csail.mit.edu/poantsai/papers/2019.zippads.asplos.pdf https://people.csail.mit.edu/poantsai/papers/2019.zippads.as.... Afaict the gist of the hotpads paper is this: Dump the existing way we organize processor caching, instead make it look like generational gc where objects can move between different caches, and pointers can be re-written to point to the new cache level that the pointee is in.

acqq 7y ago
I don't know if I understood it correctly, that their tested implementation depends on the circuits that operate faster than the cores: "We have written the RTL for these circuits and synthesized them at 45nm using yosys [55] and the FreePDK45 standard cell library [23]. The compression circuit requires an area equivalent to 810 NAND2 gates at a 2.8 GHz frequency. The decompression circuit requires an area equivalent to 592 NAND2 gates at a 3.4 GHz frequency. These frequencies are much higher than typical uncore frequencies (1-2 GHz), and a more recent fabrication process would yield faster circuits."
- Dylan16807 7y ago
  Cores are usually capable of more than 3.4GHz, and only run slower for power reasons. So a tiny circuit at that speed wouldn't be a problem. But they didn't give enough information to say how much headroom there is, with no details about how shallow/deep the circuit is or voltage or...
  - acqq 7y ago
    > and only run slower for power reasons. And if there weren't power limitations we'd already have cores using even more GHz. So a solution which depends too much on having something running faster could be not too relevant to be even used in practice. That's why I pointed to that assumption, which is I think something which has to be understood before the solution can be considered usable.
    - foota 7y ago
      Only a small part of the system runs at the higher speed, so it's not a problem for the thermal budget.
    - Dylan16807 7y ago
      600/1400 gates is so small. If that gave even a .01% boost it would be worth the energy. It's basically zero in the total power budget, even at a high clock.
  - namibj 7y ago
    Also, if this doesn't need any significant storage, there is also the option of realizing it in MCML, which kills CMOS in dynamic power and signal speed, while being very inefficient for SRAM (you don't want an L1 cache or a register file as large as current generations in that technology).
- deepnotderp 7y ago
  The "core" and "uncore" are two very different parts of a modern CPU.

by foota 7y ago

acqq 7y ago

I don't know if I understood it correctly, that their tested implementation depends on the circuits that operate faster than the cores: "We have written the RTL for these circuits and synthesized them at 45nm using yosys [55] and the FreePDK45 standard cell library [23]. The compression circuit requires an area equivalent to 810 NAND2 gates at a 2.8 GHz frequency. The decompression circuit requires an area equivalent to 592 NAND2 gates at a 3.4 GHz frequency. These frequencies are much higher than typical uncore frequencies (1-2 GHz), and a more recent fabrication process would yield faster circuits."

Dylan16807 7y ago
Cores are usually capable of more than 3.4GHz, and only run slower for power reasons. So a tiny circuit at that speed wouldn't be a problem. But they didn't give enough information to say how much headroom there is, with no details about how shallow/deep the circuit is or voltage or...
- acqq 7y ago
  > and only run slower for power reasons. And if there weren't power limitations we'd already have cores using even more GHz. So a solution which depends too much on having something running faster could be not too relevant to be even used in practice. That's why I pointed to that assumption, which is I think something which has to be understood before the solution can be considered usable.
  - foota 7y ago
    Only a small part of the system runs at the higher speed, so it's not a problem for the thermal budget.
  - Dylan16807 7y ago
    600/1400 gates is so small. If that gave even a .01% boost it would be worth the energy. It's basically zero in the total power budget, even at a high clock.
- namibj 7y ago
  Also, if this doesn't need any significant storage, there is also the option of realizing it in MCML, which kills CMOS in dynamic power and signal speed, while being very inefficient for SRAM (you don't want an L1 cache or a register file as large as current generations in that technology).
deepnotderp 7y ago
The "core" and "uncore" are two very different parts of a modern CPU.