3 ms·

Interesting. Making it run RISC-V rather than ARM would provide slightly quicker emulation, I believe. (And indeed, more generally, running a RISC-V VM provides

Interesting. Making it run RISC-V rather than ARM would provide slightly quicker emulation, I believe. (And indeed, more generally, running a RISC-V VM provides a quick way of enabling modern 64-bit code to run even on hardware that's restricted to a 32-bit address space. Given that there's a lot of such hardware around, even of quite recent vintage, this can be practically helpful.)

dmitrygr 7y ago
Riscv didn't exist when I wrote this. Even now it doesn't exist (it will "exist" when someone ships a billion somethings with it in it)
- 0815test 7y ago
  Yup, of course. Today it "exists" as a supported architecture in Linux, however... so it makes sense as a suggestion to whoever may want to try something broadly similar, but in a way that can even be practically useful. (Almost all current ISAs other than RV itself have historical warts that can slow down not just hardware implementations but emulation a lot... that's one of the reasons RV was made in the first place!)
  - cesarb 7y ago
    > Almost all current ISAs other than RV itself have historical warts RISC-V doesn't have historical warts only because it's too new for any warts it has to be considered historical. > that can slow down not just hardware implementations but emulation RISC-V shuffles the immediate bits on its instruction encoding to speed up decoding the immediate in hardware, but this slows down decoding the immediate in software. This will in the future probably be considered one of RISC-V's "historical warts".
    - 0815test 7y ago
      > RISC-V shuffles the immediate bits on its instruction encoding to speed up decoding the immediate in hardware You're right that this might be a problem, in principle. Surprisingly enough, however, RV is actually more than competitive as a system-level virtual ISA. People have experimented with this on existing emulation platforms, and that was the result they got.
- sitkack 7y ago
  I absolutely love your 8-bit Linux and plan on building one after I finish my relay computer. The billion cores mark for RISC-V will be somewhere around the middle of 2020 thanks to Western Digital and Microsemi. https://www.forbes.com/sites/tiriasresearch/2017/12/06/western-digital-gives-a-billion-unit-boost-to-open-source-risc-v-cpu/#23a62b782266 https://www.forbes.com/sites/tiriasresearch/2017/12/06/weste... > What many do not realize is that the company ships over 1 billion processor cores within its products each year and is moving toward 2 billion per year. https://hackaday.com/2019/02/13/western-digital-releases-their-risc-v-cores-to-the-world/ https://hackaday.com/2019/02/13/western-digital-releases-the... > Last year, Western Digital made the amazing claim that they will transition their consumption of silicon over to RISC-V, putting one Billion RISC-V cores per year into the marketplace. https://www.microsemi.com/product-directory/mi-v-embedded-ecosystem/4406-risc-v-cpus https://www.microsemi.com/product-directory/mi-v-embedded-ec...
  - dmitrygr 7y ago
    Oh, I do realize it. But it is 2019 so my statement holds as true :)
- johnklos 7y ago
  It exists, even without a billion somethings.

dmitrygr 7y ago

Riscv didn't exist when I wrote this. Even now it doesn't exist (it will "exist" when someone ships a billion somethings with it in it)

0815test 7y ago
Yup, of course. Today it "exists" as a supported architecture in Linux, however... so it makes sense as a suggestion to whoever may want to try something broadly similar, but in a way that can even be practically useful. (Almost all current ISAs other than RV itself have historical warts that can slow down not just hardware implementations but emulation a lot... that's one of the reasons RV was made in the first place!)
- cesarb 7y ago
  > Almost all current ISAs other than RV itself have historical warts RISC-V doesn't have historical warts only because it's too new for any warts it has to be considered historical. > that can slow down not just hardware implementations but emulation RISC-V shuffles the immediate bits on its instruction encoding to speed up decoding the immediate in hardware, but this slows down decoding the immediate in software. This will in the future probably be considered one of RISC-V's "historical warts".
  - 0815test 7y ago
    > RISC-V shuffles the immediate bits on its instruction encoding to speed up decoding the immediate in hardware You're right that this might be a problem, in principle. Surprisingly enough, however, RV is actually more than competitive as a system-level virtual ISA. People have experimented with this on existing emulation platforms, and that was the result they got.
sitkack 7y ago
I absolutely love your 8-bit Linux and plan on building one after I finish my relay computer. The billion cores mark for RISC-V will be somewhere around the middle of 2020 thanks to Western Digital and Microsemi. https://www.forbes.com/sites/tiriasresearch/2017/12/06/western-digital-gives-a-billion-unit-boost-to-open-source-risc-v-cpu/#23a62b782266 https://www.forbes.com/sites/tiriasresearch/2017/12/06/weste... > What many do not realize is that the company ships over 1 billion processor cores within its products each year and is moving toward 2 billion per year. https://hackaday.com/2019/02/13/western-digital-releases-their-risc-v-cores-to-the-world/ https://hackaday.com/2019/02/13/western-digital-releases-the... > Last year, Western Digital made the amazing claim that they will transition their consumption of silicon over to RISC-V, putting one Billion RISC-V cores per year into the marketplace. https://www.microsemi.com/product-directory/mi-v-embedded-ecosystem/4406-risc-v-cpus https://www.microsemi.com/product-directory/mi-v-embedded-ec...
- dmitrygr 7y ago
  Oh, I do realize it. But it is 2019 so my statement holds as true :)
johnklos 7y ago
It exists, even without a billion somethings.