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Verilator: Fast, Free Verilog HDL Simulator
- bpye 8y agoVerilator is an awesome tool. I suggest if you are interested in open-source EDA this you also check out Icarus Verilog [1] - an event based Verilog sim, Yosys [2] - a Verilog synthesis tool and formal solver, and NextPNR [3] - a place-and-route tool. The set of these provide a pretty reasonable set of tools for developing hardware (that is HDL) with fully open source software! [1] - http://iverilog.icarus.com/ http://iverilog.icarus.com/ [2] - http://www.clifford.at/yosys/ http://www.clifford.at/yosys/ [3] - https://github.com/YosysHQ/nextpnr https://github.com/YosysHQ/nextpnr
- bem94 8y agoThere's a longer curated list of general HDL languages and tools here: https://github.com/drom/awesome-hdl https://github.com/drom/awesome-hdl
- fxfan 8y agoAnd how does one get a cheap FPGA board out of it? China? Any recommendations?
- TD-Linux 8y agoVerilator is only a simulator, once you want to run it on a fpga you use yosys + nextpnr. The icestick is a popular and cheap choice to get started, there is also the TinyFPGA BX and iCEBreaker if you would like a few more features.
- analognoise 8y agoVerilator has some serious limitations: The driving test bench is C/C++ It is a cycle simulator, not a delta-time simulator: it will only simulate synthesizable code (not test bench code) It cannot do back-annotated timing simulations It cannot use encrypted vendor libraries (no simulations with Xilinx IP, for example) It has no mixed-HDL language capabilities It requires Gtkwave to view waveforms with (opinion, but I hate the UI) It is a terrible recommendation for beginners - you'd be much better served by using Xilinx Vivado's inbuilt simulator and waveform viewer.
- orbifold 8y agoIt has a steep learning curve, but overall I think it forces you to adopt good development practices from the start. Since it generates C++ you can also easily wrap that code and expose it to python. That way you can use software tools instead of system verilog and can easily do integration testing with your software HAL. In practice our group uses commercial tools (synopsis, cadence) and DPI-C but for the most part this is because of the VHDL code we have. Vivado‘s build in simulator is way too slow.
- q3k 8y agoThe first two are a feature for me. Not to mention not being crippled by Xilinx 'IP Core' DRM.
- analognoise 8y agoCrippled by extant, available code which is shipping in millions of devices? Is it perfect? Hell no. But it's a bit drastic to throw out an entire catalog of the most battle-tested HDL code in the world, isn't it?
- _chris_ 8y ago> It requires Gtkwave to view waveforms with (opinion, but I hate the UI) It dumps a value-change file (vcd) which can be viewed by anything, no? Sure it's not very compressed (and the compile-time for vcd-generation is unfortunate), but it's not a show-stopper.
- analognoise 8y agoThis is correct; although I am unaware of a FOSS vcd viewer which improves upon Gtkwave. I would be exceedingly happy to find one, however; please let me know.
- TD-Linux 8y agoOne cool thing you can do with Verilator is use the API to simulate other hardware. For example, here's a Verilog Gameboy being simulated realtime by simulating the display attached to it: https://twitter.com/zephray_wenting/status/1112691732393664512 https://twitter.com/zephray_wenting/status/11126917323936645...
- analognoise 8y agoYou can do this with any simulator that has a FFI interface - just use the SystemVerilog DPI.
- qalmakka 8y agoDuring my short experience with hardware design at the university I never had the chance of using Verilog. Are there advantages in using it instead of VHDL?
- Cyph0n 8y agoIn my experience, it's: 1) Less verbose and easier to write, but slightly more "error" prone (think: Java vs. Python). 2) More widely used in industry. VHDL is more heavily used in the defense industry (it came out of DoD). 3) Better support for verification (e.g., SystemVerilog).
- q3k 8y agoOpen-Source tooling support (Yosys/NextPNR flow, Yosys formal verification flow, Verilator, IVerilog). VHDL only has GHDL. And there's a bunch of small projects to translate synthesizable VHDL into Verilog (to then feed into the aforementioned tooling), but none of them are good.
- celeritascelery 8y agoThe verilator team also wrote the verilog mode for emacs. Very well done.
- jdsully 8y agoI met the author at a conference about 6 months ago. Very nice guy. Verilator is a really good way to test your designs if your building something non trivial.
- amann11 8y agoDoes anyone have links to free analog design tools?
- fest 8y agoFree as in beer-free or free as in Stallman-free? Former: LTSpice (also runs under wine). Latter: ngspice