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Since RISC-V uses Chisel instead of Verilog, you will probably need this first: https://github.com/freechipsproject/chisel-bootcamp https://github.com/freechips

Since RISC-V uses Chisel instead of Verilog, you will probably need this first: https://github.com/freechipsproject/chisel-bootcamp https://github.com/freechipsproject/chisel-bootcamp For actually learning RISC-V, you can check out these books: https://riscv.org/risc-v-books/ https://riscv.org/risc-v-books/ The Patterson and Hennessy book is a great starting point and the RISC-V reader is great reference.

dooglius 8y ago
> Since RISC-V uses Chisel instead of Verilog What do you mean? The core here is entirely Verilog/SystemVerilog
- mepian 8y ago
  I presume the parent generalized their experience with the BOOM and Rocket implementations of RISC-V, which do use Chisel, to the entire architecture.
- eBombzor 8y ago
  Sorry I am an idiot how do I edit/delete my comment so I can erase this misinformation?
  - yjftsjthsd-h 8y ago
    Unfortunately, if you don't see an edit button on the comment then you can't edit it anymore. But props for admitting you're wrong and trying to correct it :-)
chrisseaton 8y ago
> Since RISC-V uses Chisel instead of Verilog How can an ISA ‘use Chisel’? It’s a spec not an implementation.
sitkack 8y ago
The error is understandable, the main prototype RISC-V core is written in Chisel and the "Rocket Core Generator" is written in Chisel. The RISC-V team at Berkeley has a lot of overlap with the Chisel team. So it is easy to think RISC-V is all Chisel. I believe Chisel, Chisel, RISC-V, Chisel, if that makes any sense. https://riscv.org/wp-content/uploads/2015/01/riscv-rocket-chip-generator-workshop-jan2015.pdf https://riscv.org/wp-content/uploads/2015/01/riscv-rocket-ch... https://github.com/freechipsproject/rocket-chip https://github.com/freechipsproject/rocket-chip (parametric SoC generator, Chisel) https://github.com/ucb-bar/riscv-sodor https://github.com/ucb-bar/riscv-sodor (Chisel) https://chisel.eecs.berkeley.edu/ https://chisel.eecs.berkeley.edu/
- eBombzor 8y ago
  Yup I'm an idiot but I can't seem to delete or edit my original submission :c Thank you for the information.
  - sitkack 8y ago
    Ur good. Chisel.

dooglius 8y ago

> Since RISC-V uses Chisel instead of Verilog What do you mean? The core here is entirely Verilog/SystemVerilog

mepian 8y ago
I presume the parent generalized their experience with the BOOM and Rocket implementations of RISC-V, which do use Chisel, to the entire architecture.
eBombzor 8y ago
Sorry I am an idiot how do I edit/delete my comment so I can erase this misinformation?
- yjftsjthsd-h 8y ago
  Unfortunately, if you don't see an edit button on the comment then you can't edit it anymore. But props for admitting you're wrong and trying to correct it :-)

chrisseaton 8y ago

> Since RISC-V uses Chisel instead of Verilog How can an ISA ‘use Chisel’? It’s a spec not an implementation.

sitkack 8y ago

The error is understandable, the main prototype RISC-V core is written in Chisel and the "Rocket Core Generator" is written in Chisel. The RISC-V team at Berkeley has a lot of overlap with the Chisel team. So it is easy to think RISC-V is all Chisel. I believe Chisel, Chisel, RISC-V, Chisel, if that makes any sense. https://riscv.org/wp-content/uploads/2015/01/riscv-rocket-chip-generator-workshop-jan2015.pdf https://riscv.org/wp-content/uploads/2015/01/riscv-rocket-ch... https://github.com/freechipsproject/rocket-chip https://github.com/freechipsproject/rocket-chip (parametric SoC generator, Chisel) https://github.com/ucb-bar/riscv-sodor https://github.com/ucb-bar/riscv-sodor (Chisel) https://chisel.eecs.berkeley.edu/ https://chisel.eecs.berkeley.edu/

eBombzor 8y ago
Yup I'm an idiot but I can't seem to delete or edit my original submission :c Thank you for the information.
- sitkack 8y ago
  Ur good. Chisel.