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Interesting, according to Anandtech, there might be space for something else on the package: https://images.anandtech.com/doci/13829/cpu44.jpg https://images.a

Interesting, according to Anandtech, there might be space for something else on the package: https://images.anandtech.com/doci/13829/cpu44.jpg https://images.anandtech.com/doci/13829/cpu44.jpg Maybe a second Zen2 die?

Symmetry 8y ago
Or integrated graphics.
jandrese 8y ago
Probably for an iGPU for the budget model all in one chips.
DCKing 8y ago
There were some rumors before this announcement that AMD would announce SKUs with 1 CPU die (6-8 cores activated) + 1 GPU die or with 2 CPU dies (8-16 cores activated). But AMD didn't announce any SKUs - seems they're a bit behind on schedule.
- hajile 8y ago
  They are launching processors in the middle of the year. If they reveal too much 4-6 months out, Intel has way too much time to adjust their prices, change their marketing, put pressure on suppliers, etc. This leaves a lot of guesswork. Intel has to be prepared for multi-chip, chip + CPU, faster chips, slower chips (maybe this was a golden sample), etc which makes it much harder to adjust in preparation.
- okl 8y ago
  Also, if they reveal too much prospective buyers might be incentivized to delay their purchase. As stupid as that might sound, it is a thing.
  - mbroncano 8y ago
    It even has a name: Osborne effect https://en.m.wikipedia.org/wiki/Osborne_effect https://en.m.wikipedia.org/wiki/Osborne_effect
tutanchamun 8y ago
Since Rome (their server part) uses 8 chiplets for 64 cores it makes sense. When Rome was presented last year users also speculated about GPU and FPGA chiplets. Playstation 5 rumors also speculate about chiplets to keep the price to performance ratio as low as possible (though I wonder about latency which games are sensitiv to). So going all in on chiplets and reusing them for everything would make sense for AMD.
- eropple 8y ago
  I don't disagree with your takeaway, but one nit: games are less sensitive to latency than they are to unexpected latency. You can deal with latency through a number of techniques so long as it's consistent. (IIRC, this is one of the reasons for some of the interesting hardware on the Xbox 360 shrinks - reconfiguring the CPU/GPU package meant that the hardware team had to gimmick it such that games didn't have to suddenly deal with less latency than they'd been intended for.)
  - tutanchamun 8y ago
    thanks for the insight, I only ever read "games are sensitive to latency" but not exactly in what way.
    - eropple 8y ago
      No problem. Just consider it as a scheduling problem. If you know it takes N cycles to load a register (and to be clear, this is no longer something most game developers have to actively care about...though engine developers might...though on very modern consoles even this often ends up abstracted from most engine developers), having that register now be populated at (N-2) or (N+2) cycles might be Very Bad. On the other hand, if you now know that it will populate, always, in (N+4) cycles, you can just work with that.
monocasa 8y ago
Probably just keeping the chiplet orientation wrt to the iochip (as compared to their bigger products) simplify design and validation. You'd see the vias for the empty chip if it were planned to share the interposer among chip combination SKUs.
- tutanchamun 8y ago
  On /r/amd a user posted a different photo [0] taken from the stream which - to a layman like me - looks like there is circuitry (or whatever?) for a second chiplet. [0] https://i.imgur.com/gzXaoJz.png https://i.imgur.com/gzXaoJz.png
soulnothing 8y ago
On reddit there have been a lot of leaks. Pointing to either 12c or 16c variants. Additionally room for the gpu, and maybe some hbm.
- sitkack 8y ago
  > maybe some hbm Think of 3+1GB of scratch memory or L4, this could feed a GPU and not compete with main memory access. Or for notebook or game use, it would need less 100 active pins, vastly simplifying pcb design and costs.
hajile 8y ago
Take this how you will, but his leakers have been very accurate in the past. Seems possible to put 2 dies there with lower core counts to be able to use the chips (eg 4 + 4). As you say, it's also possible for 8 + 8, and probably 6 + 6 combinations. Also possible to put a GPU there for their G series. https://www.youtube.com/watch?v=PCdsTBsH-rI https://www.youtube.com/watch?v=PCdsTBsH-rI
tutanchamun 8y ago
> “Some people may have noticed on the package some extra room,” she said with a chuckle. “There is some extra room on that package and I think you might expect we will have more than eight cores.” Taken from: https://www.pcworld.com/article/3332205/amd/amd-ceo-lisa-su-interview-ryzen-raytracing-radeon.html https://www.pcworld.com/article/3332205/amd/amd-ceo-lisa-su-...

Symmetry 8y ago

Or integrated graphics.

jandrese 8y ago

Probably for an iGPU for the budget model all in one chips.

DCKing 8y ago

There were some rumors before this announcement that AMD would announce SKUs with 1 CPU die (6-8 cores activated) + 1 GPU die or with 2 CPU dies (8-16 cores activated). But AMD didn't announce any SKUs - seems they're a bit behind on schedule.

hajile 8y ago
They are launching processors in the middle of the year. If they reveal too much 4-6 months out, Intel has way too much time to adjust their prices, change their marketing, put pressure on suppliers, etc. This leaves a lot of guesswork. Intel has to be prepared for multi-chip, chip + CPU, faster chips, slower chips (maybe this was a golden sample), etc which makes it much harder to adjust in preparation.
okl 8y ago
Also, if they reveal too much prospective buyers might be incentivized to delay their purchase. As stupid as that might sound, it is a thing.
- mbroncano 8y ago
  It even has a name: Osborne effect https://en.m.wikipedia.org/wiki/Osborne_effect https://en.m.wikipedia.org/wiki/Osborne_effect

tutanchamun 8y ago

Since Rome (their server part) uses 8 chiplets for 64 cores it makes sense. When Rome was presented last year users also speculated about GPU and FPGA chiplets. Playstation 5 rumors also speculate about chiplets to keep the price to performance ratio as low as possible (though I wonder about latency which games are sensitiv to). So going all in on chiplets and reusing them for everything would make sense for AMD.

eropple 8y ago
I don't disagree with your takeaway, but one nit: games are less sensitive to latency than they are to unexpected latency. You can deal with latency through a number of techniques so long as it's consistent. (IIRC, this is one of the reasons for some of the interesting hardware on the Xbox 360 shrinks - reconfiguring the CPU/GPU package meant that the hardware team had to gimmick it such that games didn't have to suddenly deal with less latency than they'd been intended for.)
- tutanchamun 8y ago
  thanks for the insight, I only ever read "games are sensitive to latency" but not exactly in what way.
  - eropple 8y ago
    No problem. Just consider it as a scheduling problem. If you know it takes N cycles to load a register (and to be clear, this is no longer something most game developers have to actively care about...though engine developers might...though on very modern consoles even this often ends up abstracted from most engine developers), having that register now be populated at (N-2) or (N+2) cycles might be Very Bad. On the other hand, if you now know that it will populate, always, in (N+4) cycles, you can just work with that.

monocasa 8y ago

Probably just keeping the chiplet orientation wrt to the iochip (as compared to their bigger products) simplify design and validation. You'd see the vias for the empty chip if it were planned to share the interposer among chip combination SKUs.

tutanchamun 8y ago
On /r/amd a user posted a different photo [0] taken from the stream which - to a layman like me - looks like there is circuitry (or whatever?) for a second chiplet. [0] https://i.imgur.com/gzXaoJz.png https://i.imgur.com/gzXaoJz.png

soulnothing 8y ago

On reddit there have been a lot of leaks. Pointing to either 12c or 16c variants. Additionally room for the gpu, and maybe some hbm.

sitkack 8y ago
> maybe some hbm Think of 3+1GB of scratch memory or L4, this could feed a GPU and not compete with main memory access. Or for notebook or game use, it would need less 100 active pins, vastly simplifying pcb design and costs.

hajile 8y ago

Take this how you will, but his leakers have been very accurate in the past. Seems possible to put 2 dies there with lower core counts to be able to use the chips (eg 4 + 4). As you say, it's also possible for 8 + 8, and probably 6 + 6 combinations. Also possible to put a GPU there for their G series. https://www.youtube.com/watch?v=PCdsTBsH-rI https://www.youtube.com/watch?v=PCdsTBsH-rI

tutanchamun 8y ago

> “Some people may have noticed on the package some extra room,” she said with a chuckle. “There is some extra room on that package and I think you might expect we will have more than eight cores.” Taken from: https://www.pcworld.com/article/3332205/amd/amd-ceo-lisa-su-interview-ryzen-raytracing-radeon.html https://www.pcworld.com/article/3332205/amd/amd-ceo-lisa-su-...