4 ms·

Is this true on even x86? On most platforms[1] misaligned access will simply crash your program and you definitely will not execute faster (but you’ll probably

by dpark 8y ago

Is this true on even x86? On most platforms[1] misaligned access will simply crash your program and you definitely will not execute faster (but you’ll probably terminate faster). On x86 you’ll pay a hefty penalty for the misaligned access and I would expect that it likely costs more than the cache optimization saves (but maybe not). Of course you can probably optimize your struct packing anyway. Shuffling members around can get a lot of benefit without a bunch of internal padding, though you might still have some trailing padding. [1] I guess these days the platforms are essentially just x86 and ARM.

dooglius 8y ago
As long as you don't cross a cacheline boundary, I don't believe there is any misalignment penalty on recent x86/ARM processors.
- dpark 8y ago
  Interesting. I wasn’t aware that ARM allowed this at all.
  - avian 8y ago
    It really depends on architecture version and profile. Recent application profiles allow it. On microcontrollers misaligned access is still mostly forbidden as far as I know.
    - api 8y ago
      This inconsistency means you have to assume unaligned access is forbidden in portable code. Fun times.
      - tinus_hn 8y ago
        Most code is not portable at the assembler level and compiler hides this kind of detail.
        api 8y ago
        In C/C++ you can easily do stuff that violates alignment constraints unless you totally avoid casts or packed structs.
        tinus_hn 8y ago
        If what you are doing has defined behavior the compiler will make it work, although more slowly.
    - dmitrygr 8y ago
      Allowed in v7m sometimes with a one cycle penalty for data. Not allowed for code. Not allowed for some instructions ( just like x86 requires alignment for some avx inductions)
CyberDildonics 8y ago
It depends far more on memory access patterns. If memory is accessed linearly (backwards or forwards now) the prefetcher will get it for you before you get to it. Alignment matter much more when using atomics. X64 can do unaligned atomic access although (I think) there is a penalty for crossing the cache line boundary with atomics. Also there is an issue of 'false sharing' - two threads needing to sync cache lines even though the bytes they are accessing don't overlap. 128 bit (16 byte) atomic operations need to be aligned on 128 bit boundaries or they will crash. (if anyone sees something inaccurate here feel free to correct me)
- stcredzero 8y ago
  Alignment matter much more when using atomics. Someone should make a lockless library and call it, "Family." Most people will think it is a reference to the Fast and the Furious, but it would actually be a reference to Dune.
userbinator 8y ago
On x86 the effects of misalignment haven't been "hefty" since at least the 486, when they first got cache and everything within a cacheline would be just as fast --- don't forget that x86 never had aligned instruction bytes either.

by dpark 8y ago

dooglius 8y ago

As long as you don't cross a cacheline boundary, I don't believe there is any misalignment penalty on recent x86/ARM processors.

dpark 8y ago
Interesting. I wasn’t aware that ARM allowed this at all.
- avian 8y ago
  It really depends on architecture version and profile. Recent application profiles allow it. On microcontrollers misaligned access is still mostly forbidden as far as I know.
  - api 8y ago
    This inconsistency means you have to assume unaligned access is forbidden in portable code. Fun times.
    - tinus_hn 8y ago
      Most code is not portable at the assembler level and compiler hides this kind of detail.
      - api 8y ago
        In C/C++ you can easily do stuff that violates alignment constraints unless you totally avoid casts or packed structs.
        tinus_hn 8y ago
        If what you are doing has defined behavior the compiler will make it work, although more slowly.
  - dmitrygr 8y ago
    Allowed in v7m sometimes with a one cycle penalty for data. Not allowed for code. Not allowed for some instructions ( just like x86 requires alignment for some avx inductions)

CyberDildonics 8y ago

It depends far more on memory access patterns. If memory is accessed linearly (backwards or forwards now) the prefetcher will get it for you before you get to it. Alignment matter much more when using atomics. X64 can do unaligned atomic access although (I think) there is a penalty for crossing the cache line boundary with atomics. Also there is an issue of 'false sharing' - two threads needing to sync cache lines even though the bytes they are accessing don't overlap. 128 bit (16 byte) atomic operations need to be aligned on 128 bit boundaries or they will crash. (if anyone sees something inaccurate here feel free to correct me)

stcredzero 8y ago
Alignment matter much more when using atomics. Someone should make a lockless library and call it, "Family." Most people will think it is a reference to the Fast and the Furious, but it would actually be a reference to Dune.

userbinator 8y ago

On x86 the effects of misalignment haven't been "hefty" since at least the 486, when they first got cache and everything within a cacheline would be just as fast --- don't forget that x86 never had aligned instruction bytes either.