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The Mill processor architecture deserves mention here, as it basically aims to bridge VLIW-like low power usage with OOO-like performance. The way it attempts
by zozbot123 8y ago
The Mill processor architecture deserves mention here, as it basically aims to bridge VLIW-like low power usage with OOO-like performance. The way it attempts to do this is too complex to explain in a short comment, you can find detailed info on their website - but broadly-speaking it involves all sorts of 'tweaks' to ordinary VLIW, that ultimately result in something a bit different. (It should also be noted though that the initial, instruction decoding stages of a Mill-like 'belt' architecture are a lot closer to OOO than an ordinary VLIW. So the projected power savings would seemingly have to come from elsewhere - but they can be quite significant nonetheless, so the effort is projected to be worthwhile.)
- bogomipz 8y agoInteresting I remember hearing about this processor architecture. Is is still being actively developed? I didn't see much in the way of news on the Mill site.
- opencl 8y agoThere are a few recent forum posts indicating that they're still working on it at least, but it seems to be going extremely slowly. 5 years ago it had already been in development for 10 years and there was supposed to be silicon shipping in 2-3 years. 2 years ago they were talking about an FPGA prototype that has yet to show up.
- marcosdumay 8y agoI imagine (because there are not that many details on the Mill out there) that the power savings come mainly from: - A post-compiler compilation step that adapts a binary for a specific chip, replacing a complex hardware control module by a one-time software run, so the only thing actually on the chip is the routing; - A very nice set of primitives that push the non-determinism into data, instead of flow control. - Cheap interruptions, cheap memory access, and every other detail rethought to be cheap.