5 ms·

So ... here's what I'm thinking, as a complete layman with respect to how radiation affects memory devices. RAM is DRAM, i.e. dynamic RAM. It has to get autom

So ... here's what I'm thinking, as a complete layman with respect to how radiation affects memory devices. RAM is DRAM, i.e. dynamic RAM. It has to get automatically refreshed relatively frequently. So, maybe (again, me being a layman) what happens is that usually gamma rays hit a DRAM cell, but haven't imparted enough energy to cause a flip. A millisecond later the cell gets refreshed erasing what little influence the gamma ray had. No harm done. A flip would only occur if enough particles hit the cell within the refresh time frame. That's of course possible, but more rare. Contrast this with processor cache. On-die cache is most likely SRAM, Static RAM. It doesn't get refreshed. So the slight voltage errors caused by gamma rays can slowly build up over time. Perhaps this normally isn't an issue, because even though the cache is SRAM and doesn't get refreshed automatically, it'll get "refreshed" by virtue of being cache. i.e. as long as the processor is busy the cache is constantly getting re-written with new cache lines. But that won't hold true when the processor is asleep. The cache will be sitting idle, making itself susceptible to accumulated charges. Thus the likelihood of a gamma flip is greatly increased. All of that crude logic aside there's one caveat: > he workaround was removed once the problem was fixed in microcode or in a later processor stepping. So ... either everything I said is a load of bollocks and actually this was a processor bug that some CPU engineer mistook as gamma flips, or maybe my theory is correct and they changed the CPU to occasionally wake up and "refresh" its cache automatically. The mystery remains...

jimrandomh 8y ago
No, SRAM doesn't work that way. DRAM needs refreshing because it's made out of capacitors; if left alone, their charge will stay the same. Whereas SRAM is made of flip-flops; if the charge in an SRAM cell moves towards an intermediate state in between 0 and 1, it will naturally move back to 0 or 1 (whichever is closer) with no refreshing needed, by virtue of its structure.
- ip26 8y ago
  DRAM needs refreshing because it's made out of capacitors; if left alone, their charge will stay the same. No; capacitors slowly leak and lose their charge. This is why DRAM remains powered when your computer sleeps, eternally refreshing.
blattimwind 8y ago
> Contrast this with processor cache. On-die cache is most likely SRAM, Static RAM. It doesn't get refreshed. So the slight voltage errors caused by gamma rays can slowly build up over time. Static RAM is basically a flip-flop. It's a bistable circuit that's actively held in a stable state. Single-event upsets work by, essentially, putting the energy into the circuit required to make it transition into the opposite state, i.e. basically the same way the SRAM cell is written to.
- russdill 8y ago
  In layman's terms, it's being continuously refreshed.
  - throwaway2048 8y ago
    No its not, that is what makes it fundamentally different than DRAM.
    - atq2119 8y ago
      Yes, it is. That's what makes it fundamentally different from DRAM, which isn't being continuously refreshed, which is why the memory controller has to manually refresh DRAM at frequent intervals. DRAM has much simpler cells, at the cost of more complex control logic. I recommend you just take a look at Wikipedia or something for an explanation of SRAM. Each bit is typically implemented using six transistors, four of which form a loop of two inverters. They are continuously powered, which causes the continuous refresh the parent was talking about.
      - zaarn 8y ago
        There is no continuous "refresh". The circuit is bistable which means that the system has two states in which, once reached, it will remain until some energy is expended to change that. Imagine it like two valleys with a hill between. Rolling a ball from the OFF valley to the ON valley requires some energy. If it's not enough the ball rolls back into the valley it's currently in. The process is entirely analog, ie, there is no refresh circuit that looks at the voltage and says "that's almost a ON, better fresh up the voltage". The output of the circuit is digital. (You can play with the R/S latches of most SRAM on an oscilloscope and it's quite fun, the output of non-integrated SRAM will react in an analog fashion. If it's integrated, ie has a controller, this is not possible sadly) Until you cross the threshold, the circuit will simply slide back to the original position, once you cross it, it'll slide into the new position without any additional effort.

jimrandomh 8y ago

No, SRAM doesn't work that way. DRAM needs refreshing because it's made out of capacitors; if left alone, their charge will stay the same. Whereas SRAM is made of flip-flops; if the charge in an SRAM cell moves towards an intermediate state in between 0 and 1, it will naturally move back to 0 or 1 (whichever is closer) with no refreshing needed, by virtue of its structure.

ip26 8y ago
DRAM needs refreshing because it's made out of capacitors; if left alone, their charge will stay the same. No; capacitors slowly leak and lose their charge. This is why DRAM remains powered when your computer sleeps, eternally refreshing.

blattimwind 8y ago

> Contrast this with processor cache. On-die cache is most likely SRAM, Static RAM. It doesn't get refreshed. So the slight voltage errors caused by gamma rays can slowly build up over time. Static RAM is basically a flip-flop. It's a bistable circuit that's actively held in a stable state. Single-event upsets work by, essentially, putting the energy into the circuit required to make it transition into the opposite state, i.e. basically the same way the SRAM cell is written to.

russdill 8y ago
In layman's terms, it's being continuously refreshed.
- throwaway2048 8y ago
  No its not, that is what makes it fundamentally different than DRAM.
  - atq2119 8y ago
    Yes, it is. That's what makes it fundamentally different from DRAM, which isn't being continuously refreshed, which is why the memory controller has to manually refresh DRAM at frequent intervals. DRAM has much simpler cells, at the cost of more complex control logic. I recommend you just take a look at Wikipedia or something for an explanation of SRAM. Each bit is typically implemented using six transistors, four of which form a loop of two inverters. They are continuously powered, which causes the continuous refresh the parent was talking about.
    - zaarn 8y ago
      There is no continuous "refresh". The circuit is bistable which means that the system has two states in which, once reached, it will remain until some energy is expended to change that. Imagine it like two valleys with a hill between. Rolling a ball from the OFF valley to the ON valley requires some energy. If it's not enough the ball rolls back into the valley it's currently in. The process is entirely analog, ie, there is no refresh circuit that looks at the voltage and says "that's almost a ON, better fresh up the voltage". The output of the circuit is digital. (You can play with the R/S latches of most SRAM on an oscilloscope and it's quite fun, the output of non-integrated SRAM will react in an analog fashion. If it's integrated, ie has a controller, this is not possible sadly) Until you cross the threshold, the circuit will simply slide back to the original position, once you cross it, it'll slide into the new position without any additional effort.