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What's even more disappointing is that Zen 2 doesn't include support for new techs like the upcoming DDR5 & PCIe 5.0 which seems are going to be supported in Ze

What's even more disappointing is that Zen 2 doesn't include support for new techs like the upcoming DDR5 & PCIe 5.0 which seems are going to be supported in Zen 4 https://www.anandtech.com/show/13578/naples-rome-milan-zen-4-an-interview-with-amd-cto-mark-papermaster https://www.anandtech.com/show/13578/naples-rome-milan-zen-4... IC: AMD has already committed that Milan, the next generation after Rome, will have the same socket as Rome. Can you make the same commitment with Zen 4 that was shown on the roadmap slides? MP: We’re certainly committed to that socket continuity through Milan, and we haven’t commented beyond that. Obviously at some point the industry transitions to PCIe 5.0 and DDR5 which will necessitate a socket change. IC: So one might assume that an intercept might occur with Zen 4? MP: No comment (!)

Scaevolus 8y ago
PCIE 4.0 was just standardized last year, it's not surprising that Zen 2 won't support 5.0, which is expected to be introduced mid next year. Zen 2 will be the first CPUs supporting 4.0.
- shaklee3 8y ago
  Power9 was the first to support it over a year ago. But you're right, 5 is not finalized, so it's not possible for amd to support it.
- dopenmoredope 8y ago
  Release date for PCIe 5.0 is Q1 2019 Furthermore... On June 5th, 2018, the PCI SIG released version 0.7 of the PCIe 5.0 specification to its members. PLDA announced the availability of their XpressRICH5 PCIe 5.0 Controller IP based on draft 0.7 of the PCIe 5.0 specification on the same day https://www.plda.com/products/xpressrich5 https://www.plda.com/products/xpressrich5 and... Historically, the earliest adopters of a new PCIe specification generally begin designing with the Draft 0.5 as they can confidently build up their application logic around the new bandwidth definition and often even start developing for any new protocol features. At the Draft 0.5 stage, however, there is still a strong likelihood of changes in the actual PCIe protocol layer implementation, so designers responsible for developing these blocks internally may be more hesitant to begin work than those using interface IP from external sources. From here: https://en.wikipedia.org/wiki/PCI_Express https://en.wikipedia.org/wiki/PCI_Express AMD had plenty of time to include PCIe 5.0 even in the Draft 0.7 stage which is pretty much the same as final draft/release, but decided not to.
  - IntelMiner 8y ago
    Yes. AMD could have simply switched the chip over to non-finalized standards between June 5th and now. Clearly No possible way that could backfire or be impossible
  - Tuna-Fish 8y ago
    > AMD had plenty of time to include PCIe 5.0 even in the Draft 0.7 stage which is pretty much the same as final draft/release, but decided not to. ... Just how long do you think it takes to make that kind of design changes? This requires a major change in silicon. It would have had to been done more than a year ago.
    - shaklee3 8y ago
      Not to mention there are no PCIe switches with it. You'd have to wait for Avago/PLX/Broadcom/whatever it's called now to update them.
clhodapp 8y ago
Hoping for DDR 5 or PCI-E 5 support in Zen 2 is equivalent to hoping that Zen 2 is at least a 2020 architecture rather than a 2019 one. This is because: 1) PCI-E 5 isn't even standardized yet 2) Mass production of DDR5 memory chips might begin ramping up in 2019, but it's unlikely that DDR 5 memory sticks will be readily available on the market until 2020. 3) It takes a really long time to engineer a cpu architecture and bring it to market (generally a year or more for even just a revision of an existing architecture). 4) Adding support for a new memory or PCI-E version requires a new socket and a new chipset, which creates even more work that by definition can't be "done" until things are fully standardized. AMD are going to support DDR5 and PCI-E 5 eventually... But they want to release a new architecture revision on their current socket and chipset now before it's reasonably possible to do that. Edit: All this is to say nothing of AMD's commitment to potential partners to keep the underlying socket and chipset the same for a reasonable period of time, which is critical to planning supply chains and upgrade paths for major partnerships.
- Dylan16807 8y ago
  > Adding support for a new memory or PCI-E version requires a new socket and a new chipset Memory, sure, you don't want compatibility issues. Why PCIe, when the important lanes are all driven directly off the CPU?
  - clhodapp 8y ago
    Ah, fair. I guess I should say "can require".

Scaevolus 8y ago

PCIE 4.0 was just standardized last year, it's not surprising that Zen 2 won't support 5.0, which is expected to be introduced mid next year. Zen 2 will be the first CPUs supporting 4.0.

shaklee3 8y ago
Power9 was the first to support it over a year ago. But you're right, 5 is not finalized, so it's not possible for amd to support it.
dopenmoredope 8y ago
Release date for PCIe 5.0 is Q1 2019 Furthermore... On June 5th, 2018, the PCI SIG released version 0.7 of the PCIe 5.0 specification to its members. PLDA announced the availability of their XpressRICH5 PCIe 5.0 Controller IP based on draft 0.7 of the PCIe 5.0 specification on the same day https://www.plda.com/products/xpressrich5 https://www.plda.com/products/xpressrich5 and... Historically, the earliest adopters of a new PCIe specification generally begin designing with the Draft 0.5 as they can confidently build up their application logic around the new bandwidth definition and often even start developing for any new protocol features. At the Draft 0.5 stage, however, there is still a strong likelihood of changes in the actual PCIe protocol layer implementation, so designers responsible for developing these blocks internally may be more hesitant to begin work than those using interface IP from external sources. From here: https://en.wikipedia.org/wiki/PCI_Express https://en.wikipedia.org/wiki/PCI_Express AMD had plenty of time to include PCIe 5.0 even in the Draft 0.7 stage which is pretty much the same as final draft/release, but decided not to.
- IntelMiner 8y ago
  Yes. AMD could have simply switched the chip over to non-finalized standards between June 5th and now. Clearly No possible way that could backfire or be impossible
- Tuna-Fish 8y ago
  > AMD had plenty of time to include PCIe 5.0 even in the Draft 0.7 stage which is pretty much the same as final draft/release, but decided not to. ... Just how long do you think it takes to make that kind of design changes? This requires a major change in silicon. It would have had to been done more than a year ago.
  - shaklee3 8y ago
    Not to mention there are no PCIe switches with it. You'd have to wait for Avago/PLX/Broadcom/whatever it's called now to update them.

clhodapp 8y ago

Hoping for DDR 5 or PCI-E 5 support in Zen 2 is equivalent to hoping that Zen 2 is at least a 2020 architecture rather than a 2019 one. This is because: 1) PCI-E 5 isn't even standardized yet 2) Mass production of DDR5 memory chips might begin ramping up in 2019, but it's unlikely that DDR 5 memory sticks will be readily available on the market until 2020. 3) It takes a really long time to engineer a cpu architecture and bring it to market (generally a year or more for even just a revision of an existing architecture). 4) Adding support for a new memory or PCI-E version requires a new socket and a new chipset, which creates even more work that by definition can't be "done" until things are fully standardized. AMD are going to support DDR5 and PCI-E 5 eventually... But they want to release a new architecture revision on their current socket and chipset now before it's reasonably possible to do that. Edit: All this is to say nothing of AMD's commitment to potential partners to keep the underlying socket and chipset the same for a reasonable period of time, which is critical to planning supply chains and upgrade paths for major partnerships.

Dylan16807 8y ago
> Adding support for a new memory or PCI-E version requires a new socket and a new chipset Memory, sure, you don't want compatibility issues. Why PCIe, when the important lanes are all driven directly off the CPU?
- clhodapp 8y ago
  Ah, fair. I guess I should say "can require".