6 ms·

This part is a bit of a mess: "16-bit Real Mode with insruction pointer pointing to address 0xffff.fff0, the reset vector. In this initial mode, the processor

by burfog 8y ago

This part is a bit of a mess: "16-bit Real Mode with insruction pointer pointing to address 0xffff.fff0, the reset vector. In this initial mode, the processor has first 12 address lines asserted, so any address looks like 0xfffx.xxxx. This fact combined with how addressing using segment selector (SS) register works, allows the CPU to access instruction at reset vector address 0xffff.fff0" SS is the Stack Segment register. CS is for code. In real mode, the instruction pointer is only 16-bit and can not hold a value in excess of 0xffff. Ignoring those issues, the explanation still doesn't match what I've seen before in the documentation. If things have changed, when did that happen? The old explanation: The CS base is set to something like -16, that is with all but the lower 4 bits set. This covers all of physical address space, with any higher bits just being ignored. The instruction pointer is set to 0. The result is execution that starts 16 bytes below the first address that is beyond the end of the physical address space. For example, with 44-bit physical addresses this would be at 0x00000ffffffffff0.

bytefire 8y ago
yes CS not SS. i should fix that. regarding how the CPU addresses 0xffff.fff0 is not exactly specified in the post. actually CS register is loaded with 0xf000 and normally this would yield a segment selector address of 0x000f.0000 (CS left-shifted by 4 bits). but on a reset, like the post mentions, first 12 address lines are asserted so the base address ends up being 0xffff.0000. these address lines remain asserted until a long jump is made, after which the first 12 address lines are de-asserted and normal CS segment selector calculation resumes. instruction pointer contains -16 as you mentioned, the resulting address is: base address + IP = 0xffff.0000 + 0xfff0 = 0xffff.fff0 i am not sure if this is worth adding to the post but it is definitely useful.
- Sir_Cmpwn 8y ago
  By "asserted" do you mean "pinned" or "fixed"?
  - bytefire 8y ago
    sorry could you explain what pinned or fixed mean in this context. by asserted, i mean the corresponding bits being set. similar thing to when one says an interrupt line is asserted, or gpio is asserted :)
    - Sir_Cmpwn 8y ago
      "Asserted" is a past-tense verb, which implies a process of checking that it's valid at a certain moment in time, before proceeding some some work that requires it to be so. If I understand correctly (and I may not), the case is rather that the bits are always set, in which case I might call them "pinned" to 1 or "fixed" to 1 - meaning they cannot change, rather than should not change. It might also be that they are set to these values automatically during boot, but can be changed by the firmware - in which case "initialized" could be better. Or at least that's the source of confusion for me, maybe the terminology is different at this level.
      - bytefire 8y ago
        ah i see your point. here asserted defines a state and not a way of ensuring a certain condition is met (as in higher level languages). yes "initialised to 1" would also convey same meaning. i hope it's clearer now. the term asserted is often used in electronics and i can see how it can be misleading.
        Sir_Cmpwn 8y ago
        Thanks for clarifying!
      - danaliv 8y ago
        The terminology is different at this level. Asserted means the lines are set to whichever voltage is logically 1.
        0xcde4c3db 8y ago
- atq2119 8y ago
  I recall reading that it's not that those 12 bits are explicitly asserted, but rather that the CS descriptor after reset is in an "unreal mode". After all, x86 segment descriptors consist not just of their numeric value, but also of a base address, segment size, and privilege information. So at reset, CS is set to a descriptor whose numeric value is 0xf000 and whose base address is 0xffff0000, or something to that effect. All the rest follows naturally -- there's no special case logic that asserts lines of the address bus until the first long jump, it's simply that the reset value of the CS descriptor is rather magical, and that long jumps by their nature load a new CS segment descriptor which isn't magical.
  - bytefire 8y ago
    this is interesting! i am not aware of how this logic is implemented, i.e. the logic of initial state where 12 most significant bits but thanks for enlightening
    - hyperman1 8y ago
      I looked it up: https://software.intel.com/en-us/articles/intel-sdm#nine-volume https://software.intel.com/en-us/articles/intel-sdm#nine-vol... Get volume 3A and read chapter 9.1.4 at pg 315. The text is quite readable: The address FFFFFFF0H is beyond the 1-MByte addressable range of the processor while in real-address mode. The processor is initialized to this starting address as follows. The CS register has two parts: the visible segment selector part and the hidden base address part. In real-address mode, the base address is normally formed by shifting the 16-bit segment selector value 4 bits to the left to produce a 20-bit base address. However, during a hardware reset, the segment selector in the CS register is loaded with F000H and the base address is loaded with FFFF0000H. The starting address is thus formed by adding the base address to the value in the EIP register (that is, FFFF0000 + FFF0H = FFFFFFF0H). Any change to CS reverts this to normal real mode operation. So near jumps are OK, far jumps or interrupts are not.
      - monocasa 8y ago
        Practically, nearly all code I've seen pretty much immediately far jumps into 32-bit protected mode.
- burfog 8y ago
  The instruction pointer is the IP register. It is zero. It does not contain -16 or 0xfffffff0. The linear address is a different thing (computed from the CS base plus the IP/EIP/RIP content), as is the physical address. Unless something has changed in recent hardware, there aren't 12 address lines just asserted. This is a side effect of the CS base being a particular value. An important thing to realize is that x86 has hidden registers associated with segments. These registers get set when a segment selector register is loaded, not when it is used. The CS base is one of these hidden registers. If CS is loaded in protected mode, the base comes out of the descriptor table, and it remains when switching back to real mode. (this is the "unreal mode") If CS is loaded in real mode, the base comes from the selector shifted left, and this base remains even if you switch to protected mode. Switching modes doesn't change a segment base. Loading segment registers is what changes a segment base. So initially, the CS base is not set in a way that matches what you would get if you loaded the CS selector value that is seen. It is set to a value that is possibly 0xfffffff0, 0x00000ffffffffff0, 0x0000fffffffffff0, or 0xfffffffffffffff0. The older documentation I've seen would use the largest of those values. I suppose it could then be cut down to 32-bit by the bottleneck that is normally a part of addressing when not in long mode. This is the sort of area where Intel, AMD, and others may differ. Perhaps there is a hardware debugger for x86 (like a JTAG debugger) that would show the initial CS base. One could also guess that Simics or VMware might be correct, disassembling them to find out what they use. Another idea is to examine the badly-documented state used by the virtualization instructions.
  - bytefire 8y ago
    > The instruction pointer is the IP register. It is zero. it is 0xfff0, at least according to Intel Software Developer's Manual Volume 3, section 9.1.4 "First Instruction Executed". regarding 12 address lines being asserted, that is just a way of thinking about it. actual implementation might be different but what happens on reset is akin to 12 most significant bits being set. CS is 0xf000. indeed a debugger would give the right answer.
    - userbinator 8y ago
      Initial IP was 0 on the 8086/8088. I suspect that detailed technical information like this tends to be copy-pasted more than understood, which is why a lot of second-sourced information out there on it is just plain wrong or caveated. The sometimes self-contradicting information in Intel's own docs doesn't help either. This is what I've figured out from Intel's docs: 8086/88: CS:IP = FFFF:0000 first instruction at FFFF0 80186/188: CS:IP = FFFF:0000 first instruction at FFFF0 80286: CS:IP = F000:FFF0 first instruction at FFFF0 80386: CS:IP = 0000:0000FFF0 or F000:0000FFF0[1], first instruction at FFFFFFF0 80486+: CS:IP = F000:0000FFF0(?) first instruction at FFFFFFF0 [1] Depending on which datasheet/programmer's reference manual you read. I can't find any reference to someone who actually checked what the hardware did, however. More interesting reading... http://www.rcollins.org/Productivity/DescriptorCache.html http://www.rcollins.org/Productivity/DescriptorCache.html http://www.rcollins.org/ddj/Aug98/Aug98.html http://www.rcollins.org/ddj/Aug98/Aug98.html https://www.pcjs.org/pubs/pc/reference/intel/80386/loadall/ https://www.pcjs.org/pubs/pc/reference/intel/80386/loadall/
bytefire 8y ago
@burfog i have updated the post with explanation of how the reset vector address is calculated. thanks for pointing out :)
- JdeBP 8y ago
  As others here, I strongly recommend reading the IA manuals on this subject, as well as the equivalent AMD doco. Most of the processor part (but not the firmware part) of this subject is in the manufacturer doco. And yes, one has to be careful about outdated information. * https://superuser.com/a/347115/38062 https://superuser.com/a/347115/38062 * https://superuser.com/a/695716/38062 https://superuser.com/a/695716/38062 * https://superuser.com/a/345333/38062 https://superuser.com/a/345333/38062 * https://unix.stackexchange.com/a/461774/5132 https://unix.stackexchange.com/a/461774/5132

by burfog 8y ago

bytefire 8y ago

yes CS not SS. i should fix that. regarding how the CPU addresses 0xffff.fff0 is not exactly specified in the post. actually CS register is loaded with 0xf000 and normally this would yield a segment selector address of 0x000f.0000 (CS left-shifted by 4 bits). but on a reset, like the post mentions, first 12 address lines are asserted so the base address ends up being 0xffff.0000. these address lines remain asserted until a long jump is made, after which the first 12 address lines are de-asserted and normal CS segment selector calculation resumes. instruction pointer contains -16 as you mentioned, the resulting address is: base address + IP = 0xffff.0000 + 0xfff0 = 0xffff.fff0 i am not sure if this is worth adding to the post but it is definitely useful.

Sir_Cmpwn 8y ago
By "asserted" do you mean "pinned" or "fixed"?
- bytefire 8y ago
  sorry could you explain what pinned or fixed mean in this context. by asserted, i mean the corresponding bits being set. similar thing to when one says an interrupt line is asserted, or gpio is asserted :)
  - Sir_Cmpwn 8y ago
    "Asserted" is a past-tense verb, which implies a process of checking that it's valid at a certain moment in time, before proceeding some some work that requires it to be so. If I understand correctly (and I may not), the case is rather that the bits are always set, in which case I might call them "pinned" to 1 or "fixed" to 1 - meaning they cannot change, rather than should not change. It might also be that they are set to these values automatically during boot, but can be changed by the firmware - in which case "initialized" could be better. Or at least that's the source of confusion for me, maybe the terminology is different at this level.
    - bytefire 8y ago
      ah i see your point. here asserted defines a state and not a way of ensuring a certain condition is met (as in higher level languages). yes "initialised to 1" would also convey same meaning. i hope it's clearer now. the term asserted is often used in electronics and i can see how it can be misleading.
      - Sir_Cmpwn 8y ago
        Thanks for clarifying!
    - danaliv 8y ago
      The terminology is different at this level. Asserted means the lines are set to whichever voltage is logically 1.
      - 0xcde4c3db 8y ago
atq2119 8y ago
I recall reading that it's not that those 12 bits are explicitly asserted, but rather that the CS descriptor after reset is in an "unreal mode". After all, x86 segment descriptors consist not just of their numeric value, but also of a base address, segment size, and privilege information. So at reset, CS is set to a descriptor whose numeric value is 0xf000 and whose base address is 0xffff0000, or something to that effect. All the rest follows naturally -- there's no special case logic that asserts lines of the address bus until the first long jump, it's simply that the reset value of the CS descriptor is rather magical, and that long jumps by their nature load a new CS segment descriptor which isn't magical.
- bytefire 8y ago
  this is interesting! i am not aware of how this logic is implemented, i.e. the logic of initial state where 12 most significant bits but thanks for enlightening
  - hyperman1 8y ago
    I looked it up: https://software.intel.com/en-us/articles/intel-sdm#nine-volume https://software.intel.com/en-us/articles/intel-sdm#nine-vol... Get volume 3A and read chapter 9.1.4 at pg 315. The text is quite readable: The address FFFFFFF0H is beyond the 1-MByte addressable range of the processor while in real-address mode. The processor is initialized to this starting address as follows. The CS register has two parts: the visible segment selector part and the hidden base address part. In real-address mode, the base address is normally formed by shifting the 16-bit segment selector value 4 bits to the left to produce a 20-bit base address. However, during a hardware reset, the segment selector in the CS register is loaded with F000H and the base address is loaded with FFFF0000H. The starting address is thus formed by adding the base address to the value in the EIP register (that is, FFFF0000 + FFF0H = FFFFFFF0H). Any change to CS reverts this to normal real mode operation. So near jumps are OK, far jumps or interrupts are not.
    - monocasa 8y ago
      Practically, nearly all code I've seen pretty much immediately far jumps into 32-bit protected mode.
burfog 8y ago
The instruction pointer is the IP register. It is zero. It does not contain -16 or 0xfffffff0. The linear address is a different thing (computed from the CS base plus the IP/EIP/RIP content), as is the physical address. Unless something has changed in recent hardware, there aren't 12 address lines just asserted. This is a side effect of the CS base being a particular value. An important thing to realize is that x86 has hidden registers associated with segments. These registers get set when a segment selector register is loaded, not when it is used. The CS base is one of these hidden registers. If CS is loaded in protected mode, the base comes out of the descriptor table, and it remains when switching back to real mode. (this is the "unreal mode") If CS is loaded in real mode, the base comes from the selector shifted left, and this base remains even if you switch to protected mode. Switching modes doesn't change a segment base. Loading segment registers is what changes a segment base. So initially, the CS base is not set in a way that matches what you would get if you loaded the CS selector value that is seen. It is set to a value that is possibly 0xfffffff0, 0x00000ffffffffff0, 0x0000fffffffffff0, or 0xfffffffffffffff0. The older documentation I've seen would use the largest of those values. I suppose it could then be cut down to 32-bit by the bottleneck that is normally a part of addressing when not in long mode. This is the sort of area where Intel, AMD, and others may differ. Perhaps there is a hardware debugger for x86 (like a JTAG debugger) that would show the initial CS base. One could also guess that Simics or VMware might be correct, disassembling them to find out what they use. Another idea is to examine the badly-documented state used by the virtualization instructions.
- bytefire 8y ago
  > The instruction pointer is the IP register. It is zero. it is 0xfff0, at least according to Intel Software Developer's Manual Volume 3, section 9.1.4 "First Instruction Executed". regarding 12 address lines being asserted, that is just a way of thinking about it. actual implementation might be different but what happens on reset is akin to 12 most significant bits being set. CS is 0xf000. indeed a debugger would give the right answer.
  - userbinator 8y ago
    Initial IP was 0 on the 8086/8088. I suspect that detailed technical information like this tends to be copy-pasted more than understood, which is why a lot of second-sourced information out there on it is just plain wrong or caveated. The sometimes self-contradicting information in Intel's own docs doesn't help either. This is what I've figured out from Intel's docs: 8086/88: CS:IP = FFFF:0000 first instruction at FFFF0 80186/188: CS:IP = FFFF:0000 first instruction at FFFF0 80286: CS:IP = F000:FFF0 first instruction at FFFF0 80386: CS:IP = 0000:0000FFF0 or F000:0000FFF0[1], first instruction at FFFFFFF0 80486+: CS:IP = F000:0000FFF0(?) first instruction at FFFFFFF0 [1] Depending on which datasheet/programmer's reference manual you read. I can't find any reference to someone who actually checked what the hardware did, however. More interesting reading... http://www.rcollins.org/Productivity/DescriptorCache.html http://www.rcollins.org/Productivity/DescriptorCache.html http://www.rcollins.org/ddj/Aug98/Aug98.html http://www.rcollins.org/ddj/Aug98/Aug98.html https://www.pcjs.org/pubs/pc/reference/intel/80386/loadall/ https://www.pcjs.org/pubs/pc/reference/intel/80386/loadall/

bytefire 8y ago

@burfog i have updated the post with explanation of how the reset vector address is calculated. thanks for pointing out :)

JdeBP 8y ago
As others here, I strongly recommend reading the IA manuals on this subject, as well as the equivalent AMD doco. Most of the processor part (but not the firmware part) of this subject is in the manufacturer doco. And yes, one has to be careful about outdated information. * https://superuser.com/a/347115/38062 https://superuser.com/a/347115/38062 * https://superuser.com/a/695716/38062 https://superuser.com/a/695716/38062 * https://superuser.com/a/345333/38062 https://superuser.com/a/345333/38062 * https://unix.stackexchange.com/a/461774/5132 https://unix.stackexchange.com/a/461774/5132