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John Hennessy and David Patterson Turing Award Lectures (2018) [video]

93 points by espeed 8y ago

CaliforniaKarl 8y ago
John and David will be giving a talk next week Wednesday (October 10) in Stanford's Computer Systems Colloquium (EE380). The topic is Computer Architecture; the title has not yet been announced. Expect it to be up on YouTube at https://www.youtube.com/playlist?list=PLoROMvodv4rMWw6rRoeSpkiseTHzWj6vu https://www.youtube.com/playlist?list=PLoROMvodv4rMWw6rRoeSp... on Thursday or Friday next week.
chubot 8y ago
Great talk! My main takeaway is that they advocate hardware-software co-design to improve performance. Performance issues push software in the direction of domain-specific languages, and hardware in the direction of domain-specific architectures (e.g. TPUs for machine learning). I think DSLs have a lot of advantages for software engineering reasons, but not everyone agrees. But it doesn't appear to be debatable that they have advantages for performance! Previous thread: https://news.ycombinator.com/item?id=18009581 https://news.ycombinator.com/item?id=18009581 (FWIW, the research projects mentioned there count as DSLs ...)
- jacksmith21006 8y ago
  I suspect Zircon will also be similar. The next step will be to create silicon that better fits how Zircon works. Which is basically enabling breaking problems down into smaller pieces and then scheduling those pieces on different cores to work together to get a job done. Kind of enabling scaling out versus up on a SoC or in a server. With a monolithic kernel that was very difficult to do.
- yazr 8y ago
  Well hand TPU for ML is a great example (about x1000 speed improvement for tensor computation over a CPU). BUT .... TPU is just a specialized GPU which has been around for 20 years? So very slow evolution of a pre-existing HW component Deep learning has been around for 5 years and we already have 2 or 3 generation of frameworks. So very rapid revolution of DSL implemented on abstracted HW Which is the complete opposite HW-SW advocacy ?
  - yazr 8y ago
    (cont.) What maybe i am trying to say that a "sufficiently-clever-compiler" can probably make more progress in cache performance that waiting for a great new memory-cpu architecture to appear ?
ivan_ah 8y ago
Interesting off-the-cuff comments[1] about quantum computing in the question period: Patterson: You may get a question "Won't quantum computing ..." — No! Quantum computing is a really exciting; it's not going to happen tomorrow. Hennessy: It's about on the same time-scale as fusion design. [1] https://www.youtube.com/watch?v=3LVeEjsn8Ts&t=1h12m58s https://www.youtube.com/watch?v=3LVeEjsn8Ts&t=1h12m58s

93 points by espeed 8y ago

John and David will be giving a talk next week Wednesday (October 10) in Stanford's Computer Systems Colloquium (EE380). The topic is Computer Architecture; the title has not yet been announced. Expect it to be up on YouTube at https://www.youtube.com/playlist?list=PLoROMvodv4rMWw6rRoeSpkiseTHzWj6vu https://www.youtube.com/playlist?list=PLoROMvodv4rMWw6rRoeSp... on Thursday or Friday next week.

chubot 8y ago

Great talk! My main takeaway is that they advocate hardware-software co-design to improve performance. Performance issues push software in the direction of domain-specific languages, and hardware in the direction of domain-specific architectures (e.g. TPUs for machine learning). I think DSLs have a lot of advantages for software engineering reasons, but not everyone agrees. But it doesn't appear to be debatable that they have advantages for performance! Previous thread: https://news.ycombinator.com/item?id=18009581 https://news.ycombinator.com/item?id=18009581 (FWIW, the research projects mentioned there count as DSLs ...)

jacksmith21006 8y ago
I suspect Zircon will also be similar. The next step will be to create silicon that better fits how Zircon works. Which is basically enabling breaking problems down into smaller pieces and then scheduling those pieces on different cores to work together to get a job done. Kind of enabling scaling out versus up on a SoC or in a server. With a monolithic kernel that was very difficult to do.
yazr 8y ago
Well hand TPU for ML is a great example (about x1000 speed improvement for tensor computation over a CPU). BUT .... TPU is just a specialized GPU which has been around for 20 years? So very slow evolution of a pre-existing HW component Deep learning has been around for 5 years and we already have 2 or 3 generation of frameworks. So very rapid revolution of DSL implemented on abstracted HW Which is the complete opposite HW-SW advocacy ?
- yazr 8y ago
  (cont.) What maybe i am trying to say that a "sufficiently-clever-compiler" can probably make more progress in cache performance that waiting for a great new memory-cpu architecture to appear ?

ivan_ah 8y ago

Interesting off-the-cuff comments[1] about quantum computing in the question period: Patterson: You may get a question "Won't quantum computing ..." — No! Quantum computing is a really exciting; it's not going to happen tomorrow. Hennessy: It's about on the same time-scale as fusion design. [1] https://www.youtube.com/watch?v=3LVeEjsn8Ts&t=1h12m58s https://www.youtube.com/watch?v=3LVeEjsn8Ts&t=1h12m58s