Reading further: "In order to simplify an explanation, we restrict our analysis to synchronous circuits — that is, circuits in which all registers tick with the

Reading further: "In order to simplify an explanation, we restrict our analysis to synchronous circuits — that is, circuits in which all registers tick with the same clock" Sounds like the author is advocating for designs that do not have derived clocks or gated clocks or multiple clock domains -- all tricky things that designers occasionally do with great care. Clock your flip-flops with the master clock and avoid transparent latches and your design will approach the mathematical ideal that he describes when comparing a circuit to a software program. I'd guess his Lola HDL restricts you from doing some of these things, where Verilog is more YOLO depending on the vendor and warnings that are enabled.