10 ms·
AMD EPYC Performance Testing with systemd
- et2o 8y agoThis is perhaps tangential to the article, but what is the advantage of running the MySQL server with more than 48 threads on a 24-core, 48 thread CPU anyway? The fact that performance is in the EPYC cpu increasing on the older 4.13 kernel when you use 100 instead of 40 threads is surprising to me. On the Epyc (Kernel 4.15 | Ubuntu 18) and and Xeon CPU you can see it stalls or decreases from ~48 threads upwards.
- Alupis 8y agoI would assume it's because not every thread may be busy at the same time - some may be waiting for I/O, or simple keep-alive threads that only need to do things once in a while.
- igor47 8y agorunning more threads than CPUs is useful whenever your workload is not 100% CPU-bound. a DB workload is likely IO-bound, so many threads will just be sittin' there waiting to be woken up a lot of the time
- blattimwind 8y ago> no IO is performed
- Cyphus 8y agoA DB that performs no IO? Can you elaborate?
- stingraycharles 8y agoUsually that means a read-heavy workload where things fit in RAM.
- blattimwind 8y agoThat's a literal quote from the article. The benchmark was done entirely done in-memory.
- imtringued 8y agoThere is no such thing as no I/O. If you're latency bound by the round trip to main memory then SMT will still have a noticeable benefit. The most important thing it can't help with is if you are compute bound.
- BeeOnRope 8y agoNobody calls "trips to memory" I/O though. Yes SMT can have a benefit but the OP was asking about the case with more threads than logical cores, so SMT is already maxed out (assuming all threads are CPU bound).
- rbanffy 8y ago> SMT will still have a noticeable benefit YMMV. SMT usually halves the cache size usable by each thread. If your memory access is heavily local, enabling SMT can hurt your performance.
- duckerude 8y agoReferring to this sentence, I think: >To test CPU performance, I used a read-only in-memory sysbench OLTP benchmark, as it burns CPU cycles and no IO is performed by Percona Server.
- Kenji 8y agoCaching effects. If you have an x-thread CPU and you split your workload into y >> x parts, it might happen that suddenly a workload fits into a faster CPU cache level (e.g. L1 instead of L2) and then you see huge speedups. I've seen things speed up manifold when I had 67 threads and added one more even though it was an 8-thread CPU. Keep that in mind when you do threading.
- Filligree 8y agoGiven it depends on the kernel version, I would imagine some kind of platform-specific tuning. Epyc is a NUMA platform, so perhaps improvements to the NUMA scheduler? That's pure guesswork, though.
- evanelias 8y agoThe thread count in these graphs is typically on the client side -- it's the number of concurrent client threads (connections) coming from the benchmark. So with more client threads than CPU cores/HT threads, the benchmark can show the results of increasing the amount of CPU contention/saturation. On the server side, MySQL defaults to using a model of 1 thread per connection, plus various additional background threads for I/O, listening for new conns, replication, signal handling, purging old row versions, etc. Most of these are configurable, but it's not as simple as "running the MySQL server with N threads". Basically, if the benchmark is using N threads on the client side, then you can assume the server actually has N + M threads, as the server-side thread count is dynamic based on the workload.
- et2o 8y agoAh, this is the answer that makes the most sense. Thank you.
- viraptor 8y agoMost likely the change is from cgroups, and not systemd itself. This could be verified by booting with and without cgroup_disable=cpu.
- dijit 8y agoI'm not an expert, I'm a lowly systems admin- But I imagine the difference is that size of systemd itself and how mysql does fork(). SystemD is 1.5MB itself on my systems where I have it, but upstart (for example) is 148KB on centos 6. Since an AMD Epyc has roughly 64Mb of L3 Cache, a larger binary would not have to be evicted from L3 cache as often. One of Intels generally powerful all-rounder CPUs (2687Wv4) only has 30Mb of "Smart-cache" (which is fancy speak for; not that much) A complete guess on my part though..
- plantain 8y agoL1/L2/L3 Cache doesn't cache whole binaries, just hot pages from it.
- lederhosen 8y agonot hot pages, just cache lines
- dsr_ 8y agoI'm upvoting you because even though you turn out to be wrong, you appear to have been sincere about it. You shouldn't be punished, even in fake internet points, for offering a hypothesis in good faith.
- michaelmrose 8y agoI don't think imaginary internet points serve entirely or even mostly to punish. It served to highlight valuable content and in some venues to weed out low value content entirely. This is more significant in large bodies of comments. Example highlighting the most useful 20 comments out of 700. Interestingly sometimes wrong information can lead to good threads where people provide helpful corrections. In this case the thread is valuable for stirring up discussion even if the information may be wrong.
- michaelmrose 8y agoAn additional point it may be sometimes be more worthwhile to downvote incorrect information only if it seems unlikely to bear useful fruit and after providing enlightening information to the commentor if possible.
- bhouston 8y agoFun fact: a lot of user benchmarks of Ryzen Threadripper have lower averages than standard performance. For example passmark and userbench. This is because many are running TR with just 2 dimms rather than 4 dimms. This basically reduces performance by +20%. I almost think that AMD should have just not made TR work in this case because the lower than accurate benchmarks hurt then. I do not know exactly why it has this performance characteristic but I've witnessed it first hand. It is very ease to reproduce with Passmark on Windows.
- NullPrefix 8y ago4 dimm requirement seems kind of asinine. Normal systems can boot and work fine with a single stick of ram.
- bhouston 8y agoWell for high performance systems requiring 4 dimms isn't bad as the tr series has 4 memory controllers.
- tankenmate 8y agoYou don't have to run with 4 DIMMs but you'll run slower if you do; it's kinda like having a one lane road vs a 4 lane road, you can put all your traffic through one lane, but it's a whole lot slower than using four lanes.
- NullPrefix 8y agoThat was not the point I was arguing with. Let me qoute. >AMD should have just not made TR work in this case Where "this case" is <4 dimms.
- EvangelicalPig 8y agoDoes the equivalent Intel platform suffer to the same degree of performance degradation when not using all 4 memory channels?
- gsich 8y agosystemd not SystemD
- citilife 8y ago> I ran the same benchmark on my Intel box What was the Intel box? I'm also wondering the EPYC system was configured properly.
- aoeusnth1 8y agoIt was listed in the first few paragraphs, Intel(R) Xeon(R) CPU E5-2680 v3 @ 2.50GHz
- rossmohax 8y agoI am pretty sure it has something to do with kernel.sched_autogroup_enabled = 1 which places process from different sessions into different scheduling groups.Bash terminal is session leader and all processes are part of it, unless they explicitly break away with setsid(2) call
- nisa 8y agoFound some more details here: https://www.postgresql.org/message-id/50E4AAB1.9040902@optionshouse.com https://www.postgresql.org/message-id/50E4AAB1.9040902@optio...
- dragontamer 8y agoIts the infinity fabric. AMD EPYC doesn't have 64MB of L3 cache. It has 8x8MB of L3 cache. * If CCX#0 has a cacheline in the E "Exclusive Owner" state, then CCX1 through CCX7 all invalidate their L3 cache. There can only be one owner at a time, because the x86 architecture demands a cohesive memory. * All 8-caches can hold a copy of the data. In the case of code: this means your code is replicated 8x and uses 8x more space than you think it does. Code is mostly read-only. With that being said, it is shared extremely efficiently, as all 8x L3 caches can work independently. (1MB of shared code on all 8x CCXes will use up 8x1MB of L3). * Finally: if CCX#0 has data in its L3 cache, then CCX#6 has to do the following to read it. #1: CCX#6 talks to the RAM controller, which notices that CCX#0 is the owner. The RAM controller then has to tell CCX#0 to share its more recent data (because CCX#0 may have modified the data) to CCX#6. This means that L3-to-L3 communication has higher latency than L3-to-RAM communication! ------------- In the case of a multithreaded database, this means that a single multithreaded database will not scale very well beyond a CCX (12-threads in this case). L3-to-L3 communications over infinity fabric is way slower, because of the cache coherence protocols that multithreaded programmers rely upon to keep the data consistent. But if you run 8x different benchmarks on the 8x different CCXes... each of which were 12-thread each, it would scale very well. ------------- Overall, the problem seems to scale linearly-or-better up to 16ish threads. (8x is 6762.35, 16x is 13063.39). Scaling beyond 6-threads is technically off a CCX (3-cores per CCX on the 7401), but remains on the same die. There's internal infinity fabric noise, but otherwise the two L3 caches inside a singular die seem to communicate effectively. Possibly, the L3->memory controller->L3 message is very short and quick, as its all internal. The next critical number for the 7401 is 12-threads, which is off of a die (3+3 cores per die). This forces "external" infinity fabric messages to start going back and forth. Going from 12-threads (10012.18) to 24-threads (16886.24) is all the proof I need. You just crossed the die barrier, and can visibly see the slowdown in scaling. -------------- With that being said, the system looks like it scales (sub-linearly, but its still technically better) all the way up to 48 threads. Going beyond that, Linux probably struggles and begins to shift the threads around the CCXes. I dunno how Linux's scheduler works, but there are 2x CCXes per NUMA node. So even if Linux kept the threads on the same NUMA node, they'd have to have this L3 communication across infinity fabric if Linux inappropriately shifted threads between say... Thread#0 and Thread#20 on NUMA #0. That kind of shift would rely upon a big L3-to-L3 bulk data transfer across the two different CCXes (although, on the same die). I'd guess that something like this is going on, but its completely speculation at this point.
- newnewpdro 8y agoImplying that systemd is somehow the root-cause for this performance disparity strikes me as ridiculous. I've noticed a pattern over the years with anyone spelling systemd as SystemD: They tend to not really know what the hell they're talking about with regards to systemd, while possessing significant bias against the project, actively searching for reasons to disparage it.
- snorrah 8y agoFeel free to illuminate us with what the possible performance discrepancy is instead caused by ?
- viraptor 8y agoCould be phrased better, but they're not wrong: https://news.ycombinator.com/item?id=17518518 https://news.ycombinator.com/item?id=17518518
- newnewpdro 8y agoA kernel bug, that systemd exposes by attempting to utilize more of the kernel's newer features.