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I don't quite get the open source angle in the comments here. If I managed to get my grubby hands on a moderately modern computer, I can use all manner of open

I don't quite get the open source angle in the comments here. If I managed to get my grubby hands on a moderately modern computer, I can use all manner of open source software and I can create wonderful new software. The barrier of entry is fairly low in rich countries. If AMD open sourced all the design aspects of their chips, I would have to get a loan to build 100 million fab to have any practical manner to enjoy it? I can see that if Intel/AMD/NVidia/Apple shared all aspects fo their chips cross pollination might bring great things, and academic research would be boosted and might end up giving back more to the community at large, but you are talking about very few entities across the world that can afford fabs.

civilitty 8y ago
> If AMD open sourced all the design aspects of their chips, I would have to get a loan to build 100 million fab to have any practical manner to enjoy it? Try $1 to 5 billion. We're talking about something that over half of all extant nation states wouldn't be able to pull off without devoting 10-50% of their annual GDP to the project.
- solarkraft 8y ago
  Even the large designers (AMD, Apple, Mediatek) don't have their own fabs. You would "just" need to order a design made - probably for hundreds of thousands of chips to make any sense. Is there information on what this step would actually require?
  - civilitty 8y ago
    First, you have to choose your feature size and manufacturer based on your specs because that will lock down your available cell library. Cell libraries are an abstraction over the masks/dopants and describe how to fab the transistors and higher level logic gates, made by each manufacturer for each feature size. STM, TSMC, Global Foundries, etc. have their own cell libraries and each process node gets a different one (there could also be different libraries for consumer, medical, automotive, etc.). If your design isn't pushing the physical limits of your chosen process, you can usually use a standard cell library supported by your synthesizer so that you can stay in HDLs instead of tweaking masks. Once you've finished your design (I'll leave this as an exercise to the reader :)), you'll start a back and forth with the foundry which will run its own database of rules against your design and work with you to make tweaks that better fit their fab. After you agree on a final mask, you and the fab will run verification simulations and eventually, after several months, you'll get your chips with that new factory smell. Yes, you can "just" order some chips made. I don't have the URLs off the top of my head but there are a few companies here in California that I've worked with. You can literally walk into their offices unannounced and if you have the money, they will start right then and there. If I remember correctly, in 2012 it cost about $100k to get started with STM's 45nm process (might have been 28nm by then, don't remember). Today, 28nm can cost as low as $4-12k if you're a Canadian researcher [1] - although that's almost certainly subsidized. It all seems scary only because the process is so complex that no one person has a grasp on even a minor fraction of what's going on. [1] https://www.cmc.ca/en/WhatWeOffer/Products/CMC-00200-02843.aspx https://www.cmc.ca/en/WhatWeOffer/Products/CMC-00200-02843.a...
    - nickpsecurity 8y ago
      There's also S-ASIC's like eASIC provides on 45nm and 28nm. What do you think about that in today's market? (No affiliation. I find this option interesting with the varied responses I get on the topic. Triad Semi was another interesting option in this space.)
      - civilitty 8y ago
        I've only ever made ASICs for high power RF equipment and that was using large feature sizes (>180 nm) in the 90s. I don't think structured ASICs even existed at that point so I can't offer any insights. The idea is really cool. My go to advice: know your specs, know your vendor, know your delivery guy. If you can implement your design within the restrictions of your chosen structured ASIC, you trust the vendor to deliver on time/in quantity, and you can get them soon enough (I don't know the turn around time) then go for it.
  - kragen 8y ago
    Civilitty's answer is good, but I think the $4–$12k price is not subsidized; it's just CMP’s normal price. Older process nodes are even cheaper. MOSIS is the US equivalent of CMP. I don't know what the Chinese equivalent is but I am sure there is one. This is a process a substantial number of undergraduate students manage to get through in a semester each year. Some universities will foot the MOSIS or CMP bill if the design passes DRCs. You don't have to build your own fab or even get a fab to dedicate a whole wafer to you.
  - arbie 8y ago
    If you are willing to share silicon space with other chips, you can prototype chips on older nodes (e.g., 14nm) through services like MOSIS for "just" tens of thousands of dollars: https://www.mosis.com/products/fab-schedule https://www.mosis.com/products/fab-schedule
s3krit 8y ago
The argument to share your source code extends beyond the argument that the average end-user can take that code, alter it and redistribute it. The bar for entry for contributing to hardware is not 'has their own multi-billion dollar fab center'.
ur-whale 8y ago
I believe you have it backwards: this is exactly why there is actually very little risk for the big guys to actually share their knowledge. The financial entry barrier for building a fab is so huge that what in heaven's name would intel lose if they published the RTL for - say - their integer division hardware to show and teach the whole world how it's done when real professionals take a stab at it? And if they're scared AMD might copy their integer division, why not publish the Verilog code from 2 or 3 generation old h/w? (and this is probably a bad example, I believe AMD and Intel are essentially done competing on stuff like that). But what I am talking about here is basically unthinkable given the current culture in the EDA world: a person suggesting this inside one of the big shops would be committing career suicice. Conversely, if you navigate EDA discussion boards a little bit, there is no end to the snarky or sometimes downright insulting comments made by big shop insiders about how lame and terribly inefficient the open source hardware designs published on the net actually are. In other words: mocking outsiders are their ignorance instead of teaching them how to do cool stuff. That's the culture of the EDA world. Time for a change.
- et2o 8y ago
  What are the EDA discussion boards? Curious to peruse.
  - ur-whale 8y ago
    Here's one: https://www.edaboard.com/ https://www.edaboard.com/
tasty_freeze 8y ago
Nvidia did release an open source deep learning core: RTL, c models, regression tests. http://nvdla.org/index.html http://nvdla.org/index.html The source code is on github.

civilitty 8y ago

> If AMD open sourced all the design aspects of their chips, I would have to get a loan to build 100 million fab to have any practical manner to enjoy it? Try $1 to 5 billion. We're talking about something that over half of all extant nation states wouldn't be able to pull off without devoting 10-50% of their annual GDP to the project.

solarkraft 8y ago
Even the large designers (AMD, Apple, Mediatek) don't have their own fabs. You would "just" need to order a design made - probably for hundreds of thousands of chips to make any sense. Is there information on what this step would actually require?
- civilitty 8y ago
  First, you have to choose your feature size and manufacturer based on your specs because that will lock down your available cell library. Cell libraries are an abstraction over the masks/dopants and describe how to fab the transistors and higher level logic gates, made by each manufacturer for each feature size. STM, TSMC, Global Foundries, etc. have their own cell libraries and each process node gets a different one (there could also be different libraries for consumer, medical, automotive, etc.). If your design isn't pushing the physical limits of your chosen process, you can usually use a standard cell library supported by your synthesizer so that you can stay in HDLs instead of tweaking masks. Once you've finished your design (I'll leave this as an exercise to the reader :)), you'll start a back and forth with the foundry which will run its own database of rules against your design and work with you to make tweaks that better fit their fab. After you agree on a final mask, you and the fab will run verification simulations and eventually, after several months, you'll get your chips with that new factory smell. Yes, you can "just" order some chips made. I don't have the URLs off the top of my head but there are a few companies here in California that I've worked with. You can literally walk into their offices unannounced and if you have the money, they will start right then and there. If I remember correctly, in 2012 it cost about $100k to get started with STM's 45nm process (might have been 28nm by then, don't remember). Today, 28nm can cost as low as $4-12k if you're a Canadian researcher [1] - although that's almost certainly subsidized. It all seems scary only because the process is so complex that no one person has a grasp on even a minor fraction of what's going on. [1] https://www.cmc.ca/en/WhatWeOffer/Products/CMC-00200-02843.aspx https://www.cmc.ca/en/WhatWeOffer/Products/CMC-00200-02843.a...
  - nickpsecurity 8y ago
    There's also S-ASIC's like eASIC provides on 45nm and 28nm. What do you think about that in today's market? (No affiliation. I find this option interesting with the varied responses I get on the topic. Triad Semi was another interesting option in this space.)
    - civilitty 8y ago
      I've only ever made ASICs for high power RF equipment and that was using large feature sizes (>180 nm) in the 90s. I don't think structured ASICs even existed at that point so I can't offer any insights. The idea is really cool. My go to advice: know your specs, know your vendor, know your delivery guy. If you can implement your design within the restrictions of your chosen structured ASIC, you trust the vendor to deliver on time/in quantity, and you can get them soon enough (I don't know the turn around time) then go for it.
- kragen 8y ago
  Civilitty's answer is good, but I think the $4–$12k price is not subsidized; it's just CMP’s normal price. Older process nodes are even cheaper. MOSIS is the US equivalent of CMP. I don't know what the Chinese equivalent is but I am sure there is one. This is a process a substantial number of undergraduate students manage to get through in a semester each year. Some universities will foot the MOSIS or CMP bill if the design passes DRCs. You don't have to build your own fab or even get a fab to dedicate a whole wafer to you.
- arbie 8y ago
  If you are willing to share silicon space with other chips, you can prototype chips on older nodes (e.g., 14nm) through services like MOSIS for "just" tens of thousands of dollars: https://www.mosis.com/products/fab-schedule https://www.mosis.com/products/fab-schedule

s3krit 8y ago

The argument to share your source code extends beyond the argument that the average end-user can take that code, alter it and redistribute it. The bar for entry for contributing to hardware is not 'has their own multi-billion dollar fab center'.

ur-whale 8y ago

I believe you have it backwards: this is exactly why there is actually very little risk for the big guys to actually share their knowledge. The financial entry barrier for building a fab is so huge that what in heaven's name would intel lose if they published the RTL for - say - their integer division hardware to show and teach the whole world how it's done when real professionals take a stab at it? And if they're scared AMD might copy their integer division, why not publish the Verilog code from 2 or 3 generation old h/w? (and this is probably a bad example, I believe AMD and Intel are essentially done competing on stuff like that). But what I am talking about here is basically unthinkable given the current culture in the EDA world: a person suggesting this inside one of the big shops would be committing career suicice. Conversely, if you navigate EDA discussion boards a little bit, there is no end to the snarky or sometimes downright insulting comments made by big shop insiders about how lame and terribly inefficient the open source hardware designs published on the net actually are. In other words: mocking outsiders are their ignorance instead of teaching them how to do cool stuff. That's the culture of the EDA world. Time for a change.

et2o 8y ago
What are the EDA discussion boards? Curious to peruse.
- ur-whale 8y ago
  Here's one: https://www.edaboard.com/ https://www.edaboard.com/

tasty_freeze 8y ago

Nvidia did release an open source deep learning core: RTL, c models, regression tests. http://nvdla.org/index.html http://nvdla.org/index.html The source code is on github.