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Is decreasing the spacing of gates and increasing the density of chips the only way to squeeze more performance out of chips?
by theshadowknows 8y ago
Is decreasing the spacing of gates and increasing the density of chips the only way to squeeze more performance out of chips?
- ecarrick 8y agoNot necessarily. Parallelization has allowed better performance from chips. Adding more cores has allowed better throughput but the benefits are seen more on the application side. They could make the chips bugger, but the problem with expanding outward is the routes connecting the transistors become too long and suffer increased time delay due the increased resistance of the long line. Without being able to make chips larger the only way to get better physical performance is to increase density.
- marcosdumay 8y agoIt's not just decreasing spacing. It's decreasing wire resistance and gate capacitance. That's what makes the most difference. It is also about making things cheaper, because your costs are constant for a wafer, but the use is measured by gate count. That said, things are not that simple for a long time already.
- deepnotderp 8y agoWire and contact resistance has been steadily increasing and FinFETs actually increased gate capacitance.
- marcosdumay 8y agoAs I said, things have not been that simple for a time.
- no_identd 8y agoWell we could switch everything to balanced ternary (which has a higher radix economy not just than binary, but also than unsigned ternary. Something most people talking about ternary neglect to mention - because the traditional formula for calculating radix economy isn't generalized.), but that comes with a heap of other (tractable!) problems...
- IWeldMelons 8y agoTernary does not bring enough of difference in terms of efficiency, just 1.5 times or so.