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FPGAs becoming more SoC-like
- lnsru 8y agoNo. There is a more suitable tools now for every problem. Large volume - ASIC, and you can also put few ARM cores inside. Something highly integrated - pick ZynQ. There are dozen different solutions for all the problems starting with big FPGA with couple softcore processors going to cheap spartan 7 device and going to tiny and dirt cheap Lattice chip for glue logic or IO expansion. Tools might be better, but this problem will be solved in the future for sure.
- arghwhat 8y agoIt wasn't a question. ASIC isn't the tool for large volume, it's the tool for when you can accept a several year turnaround time for revisions, vs. a day or two. ASIC > FPGA... except if your design changes, ever. If anything high-bandwidth or design intensive is going on, you're definitely going to revise your design many times. FPGA's are massively on the rise (although slightly less so than Xilinx would like), and they all are effectively "SoC like", with DSPs, transceivers, hard IP's probably being a majority of the chip by now. Zynq is a cute little chip, but with Intel's coming CPU-embedded FPGA's, thing will kick off even more.
- codeflo 8y agoWhat's the tooling like for a typical, production-quality FPGA project nowadays? Last I checked, which is admittedly a couple of years ago (and I didn't dive in very deeply), it was a horrible mix of badly programmed vendor-specific Windows-only GUI tools. It seemed a lot like the embedded processor market where every single vendor has their own lock-in strategy and the whole ecosystem suffers for it. Has this improved in the meantime?
- tails4e 8y agoVivado us actually very good for EDA, and especially for one you can get for free (webpack). Compare it to design compiler for basic synthesis- now that is an ugly gui! Vivado had made great strides to integrate ip/rtl/synthesis/pnr/debug with cross probing between stages and great visual presentation of results. Try do any of this with 'industry standard' tools like design compiler and you will see just how good it is comparatively.
- lnsru 8y agoThe colleagues are telling me, that this ugly GUI works nowadays under Linux too. You also can script much using tcl commands. I have it running on Windows and it works somehow, but I am not happy user:-/
- xfer 8y agoXilinx Vivado is not ugly; but resource heavy; so most people stick to tcl scripting.
- tails4e 8y agoAgreed it's a very well designed gui, but seems to gobble memory. If you have a 32gb linux machine it's excellent.
- lnsru 8y agoGoing from IP catalog to pin planner is not the easiest task. Or setting bitstream properties. Some settings are accessible from special locations, and this isn’t very intuitive. It’s easy when you know all these details.
- arghwhat 8y agoI'd argue that it's both ugly and resource heavy, but "ugly" would be a matter of taste. I just have a very strong aversion for IDE's that fail to prioritize text editing, permanently wasting space on all sorts of buttons and knobs that are only needed 0.1% of the time. It doesn't help that they often also fail to be responsive.
- moftz 8y agoI don't write much VHDL or Verilog for my work. Most of it is combining cores together that are either from the vendor or are generated using Simulink. Occasionally there needs to be some glue logic to link some blocks together and all the code in the softcore processor needs to be written in C but most of the development is based on wiring up blocks in Libero's GUI.
- pjc50 8y agoIt's still like that. It's an extremely conservative industry.
- setquk 8y agoTooling is cheaper and more reliable at least. Honestly I find the situation better than 20 years ago now on the embedded processor front. The worst thing we have now is broken shitty standard libs and compilers. You can dodge around those by picking assembly (PIC for example, mpasm is actually ok) or platforms with GCC implementations (ARM/AVR)
- aylons 8y agoWindows only tools? You must have been using Altera options (I briefly maintained the page for Quartus compatibility at wine, circa 2004). Even them have had Linux support for a while, Xilinx has Linux support for as far as I remember, at least some ten years. The ecosystem is terrible, I agree with you. However, the lock in is restricted for the final synthesis part. Simulation is mostly done with (very expensive) third party tools, such as Mentor Graphics Modelsim, and in professional settings the build is automated to a point that opening the vendor's GUI is frowned upon. There are some quality open sources tools on FPGA build automation, but most places I had contact with have their own internal tools.
- stochastic_monk 8y agoI know someone who’s implemented some string algorithms for FPGA with verilog. Is writing the code distinct from the tooling you’re referring to, or simply an open source flavor of deployment? I haven’t done any FPGA work.
- deleted 8y ago[deleted]
- aylons 8y agoWhen he talks about Verilog, he is referring to the language used for development and implementation. We're talking about a different part of the chain, something akin to the compiler, make, cmake and alike. Of course, there's some dynamic between the tool chain and the language itself. For example, it doesn't matter if the language has the coolest feature if the compiler does not support it, and the toolchain will help you manage more complex code safely.
- orbifold 8y agoAll the FPGA tools by Xilinx work well under Linux and Vivado is actually quite pleasant to use. Almost all of the EDA tools can be scripted with TCL (cadence has a host of other DSL aswell) so you don’t need to use the GUI if you don’t want to.
- arghwhat 8y agoVivado is absolutely terrible, especially the GUI. Our toolchain at work is set up so that it can be entirely avoided, with developers only writing Verilog in their editor of choice, and calling make or pushing to Jenkins when they want results. And then they go home, as it takes a full day to build a product on our server farm. Sim/others is done with third-party products. I recall one Xilinx event where a Xilinx presenter asked how many people were using the Vivado IDE for development. IIRC, only a single hand was held up. Vivado isn't worse than the competition, though. Intel/Altera's offering is also a steaming pile of crap (we evaluate the competing platform every once in a while when we decide what FPGAs to use for new products). I don't know why all FPGA tooling sucks, but it does.
- xu3kev 8y agoWriting Verilog in the editor of choice then calling make and pushing to Jenkins sounds amazing. Could you elaborate further on the methods and best practices to develop FPGA without Vivado IDE?(As your story indicate that there are many people can do this in the industry.) I'd like to know more about the setup.
- planteen 8y agoAnd don't get me started on trying to version control a Vivado project. It's like they didn't even consider the possibility of committing a project to source control! I last used Vivado about 2 years ago but doubt things have changed much. It really makes me wonder how Xilinx does it in-house.
- matt_the_bass 8y agoI was just about to say this! We’ve recently hacked our Vivado project into git. This requires unpacking all packages and ignoring compiled packages. Plus a bunch of bat files to handle house keeping. A big part of the issue is compiling packages. I think this is a thing because synthesis takes so long. Until synthesis time is reduced, I think we’ll see these hack-y solutions.
- baybal2 8y agoLattice was the one
- arghwhat 8y agoWell, it certainly hasn't been Windows specific for over a decade, but it's definitely bad. Comparing it to software development toolchains, one might even go as far as calling it a steaming pile of horsedung. However, a lot of it can be hidden, making the flow: 1. Write verilog in your editor of choice, 2. Call make. 3. Come back tomorrow to check the result.
- oneplane 8y agoBut isn't it becoming more like "SoCs gaining FPGA cores"? I know traditional FPGAs got hard CPU cores added, but from the CPU perspective the FPGA core is the new thing.
- kingosticks 8y agoThis article mentions that but doesn't give any details. Annoying since that's the interesting bit.
- thesz 8y agoArticle says "CPU does not fit FPGA synthesis very well and uses almost whole thing". People serious about prototyping usually get daughterboards for FPGA and/or FPGA stacks specifically to prototype big things with CPUs. The buses can go outside of main FPGA with CPU and into other things. I know at least one big SoC project which went that way. I also think that having an ARM core in FPGA is a vendor lock in. For example, you cannot use AMBA/APB/AXB and other ARM buses with ARM CPU core in your design without paying ARM for license for these buses. It is not clear to me whether Zynq users have to pay for these buses and it may be case that they have to. Finally, ARM core in the prototype naturally extends into ARM core in the final product. ARM itself is not very nice design from contemporary point of view. I expressed my dissatisfaction with ARM ISA many times here and just let me start with two points: 1) ARM is not RISC (multiregister load/store execute in several clocks) and 2) too much of initial design of first ARM (which was not planned for longterm evolution) is visible in ISA. Basically, they put outdated (even for 2010) core design and used valuable silicon area so users have to use that instead of much more capable contemporary designs. Instead of trying to figure out how to change typical FPGA elements and layouts for CPUs to be more synthesable (which may bring benefits in other places), they decided to use that ARM thing. I am deeply disappointed with that path.
- adwn 8y ago> ARM itself is not very nice design from contemporary point of view. [...] they decided to use that ARM thing ARM CPUs are the de-facto standard in the embedded world (except for simple 8-bit MCUs), so what should Xilinx have done? Design their own, proprietary CPU architecture and ISA? Choose some other architecture with 2% market share? Both paths would have led to the immediate death of the whole product line. > 1) ARM is not RISC (multiregister load/store execute in several clocks) So? Who cares? > 2) too much of initial design of first ARM (which was not planned for longterm evolution) is visible in ISA. Ah, yes, technological purism – the quickest way to practical irrelevance.
- planteen 8y ago> ARM CPUs are the de-facto standard in the embedded world (except for simple 8-bit MCUs), so what should Xilinx have done? Design their own, proprietary CPU architecture and ISA? Choose some other architecture with 2% market share? Both paths would have led to the immediate death of the whole product line. Totally agree. IIRC, didn't Xilinx have another hard core CPU+FPGA design before the Zynq using a PowerPC? PPC is largely irrelevant these days. The high-performance embedded space is dominated by ARM today with x86 and PPC taking the rest. There's no way Xilinx would choose x86 with Intel owning Altera. Maybe in 5-10 years RISC-V will start to eat some of ARM's share, but that remains to be seen.
- stochastic_monk 8y agoWhat does SoC stand for? I’m assuming not Summer of Code.
- detaro 8y agohttps://en.wikipedia.org/wiki/System_on_a_chip https://en.wikipedia.org/wiki/System_on_a_chip
- stochastic_monk 8y agoThank you! I couldn’t find anything in the article.
- madengr 8y agoYeah, took me several articles until I found out that the SD means Software Defined. Irks me when articles don’t define acronyms.