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From The Next Platform (https://www.nextplatform.com/2018/05/24/a-peek-inside-that-intel-xeon-fpga-hybrid-chip/ https://www.nextplatform.com/2018/05/24/a-peek-i
by sehugg 8y ago
From The Next Platform (https://www.nextplatform.com/2018/05/24/a-peek-inside-that-intel-xeon-fpga-hybrid-chip/ https://www.nextplatform.com/2018/05/24/a-peek-inside-that-i...):
The initial workload that Intel is targeting is putting Open Virtual Switch, the open source virtual switch, on the FPGA, offloading some switching functions in a network from the CPU where such virtual switch software might reside either inside a server virtualization hypervisor or outside of it but alongside virtual machines and containers. This obviates the need for certain Ethernet switches in the kind of Clos networks used by hyperscalers, cloud builders, telcos, and other service providers and also frees up compute capacity on the CPUs that might otherwise be managing virtual switching. Intel says that by implementing Open Virtual Switch on the FPGA, it can cut the latency on the virtual switch in half, boost the throughput by 3.2X, and crank up the number of VMs hosted on a machine by 2X compared to just running Open Virtual Switch on the Xeon portion of this hybrid chip. That makes a pretty good case for having the FPGA right close to the CPU – provided this chip doesn’t cost too much.
- mtgx 8y agoThat seems like a weak benefit. I don't think the fpga part will be cheap. In fact it will probably be significantly more expensive than the CPU. So then why not buy a chip with twice the cores if running twice the VMs is what you want to do with it? Also you can buy an AMD EPYC chip with twice the cores for about the same price you'd pay only for the CPU part of this chip/half the intel cores.
- baybal2 8y ago>Also you can buy an AMD EPYC chip with twice the cores for about the same price you'd pay only for the CPU part of this chip/half the intel cores. Indeed. What benefits the most from being turned into FPGA circuit are stateless or minimally stateful circuits like media decoders/encoders. Complex stuff like fancy routers, classifiers, internet protocol inspection/handling will not gain a hundredfold speedup unlike the stuff above. This is why cheap x86 based routers are still a thing. At the moment, I am involved with one cloud provider in China that bids big on cheap FPGAs and RDMA. AWS and Azures can be defeated in detail. The plan is following: provide hardware accelerated "building blocks" of any modern dotcom business. Need memcached? We have it running on RDMA, from a bare metal ASIC, 10 times faster than any x86. Need transcoding? We have it available on RDMA, from a bare metal ASIC, 10 times cheaper than any AWS instance on buck/megabyte. Need API proxy for TLS/Gzip with gigabytes per second throughput? We have it running on RDMA, from a box with 4 PCIe accelerators, and AWS has nothing to offer for this use case other than "buy a hundred of top tier high performance instances and put them behind load balancers"
- guiriduro 8y agoPretty sure AWS has had f1 instances for some time already.
- baybal2 8y agoYeah, but for those one you still have to do all the HDL programming stuff yourself. Alibaba on other hand aims to provide everything ready to use over a cute RDMA api
- bogomipz 8y ago>"At the moment, I am involved with one cloud provider in China that bids big on cheap FPGAs and RDMA. AWS and Azures can be defeated in detail." Can you share how this FPGA and RDMA combination works architecturally? What's the software stack composed of? Might you have any links or other resources you could share?
- baybal2 8y agoMade almost entirely in house. You provision access over in-dc REST api, then rdma capable routers route the appliance to your vm, then you access it through provided libs for linux. In other words, you don't deal with RDMA yourself at any moment
- segmondy 8y agoFolks that need this don't care about the expense. it's about the pipeline between the CPU and FPGA. If it's 5-10x as fast as plugin FPGA, There will be a market.
- gautamdivgi 8y agoDepends on the functional area. It will be a huge boost for virtual networking especially for virtual network functions. I personally know of cases where we have to wrangle with sr-Iov and dpdk. I will be super interested in the ovs fpga
- jandrese 8y agoThere could be a win if the FPGA part is efficient. Power and heat are a limiting factor for rack density, and this could allow you to run more machines in a rack than you could otherwise support. Pretty narrow still, but the market segment is possibly real.
- euroclydon 8y agoCould this help out in the HFT userland-networking scene?